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ES-203 Computer Oraganization & Architecture CNN on FPGA board

Overview

Video Demostration

Computer Organization & Architecture CNN Machine learning project on FPGA board | ES 203 Project

Vivado files

Main Verilog CNN file

Tips for LUT Optimization

Here, I am mentionaing some methods for converting your C type for-loops into efficient always blocks with chaining one to another

1: How to convert a for loop into verilog always block

// C code
for(int i = 0; i<n; i++)
{
	operations and functions
}

Same process implemented using always a block & a flag

integer i = 0, flag = 0;
...code
{ flag = 1; }	// when required
always@(posedge clock)
if(flag)
begin
		if(i==n) flag = 0;
		else
	begin
		operations and functions
		i = i+1;
	end
end

2: How to convert Nested for-looping into verilog always block

// C code
for(int i = 0; i<m; i++)
{
		for(int j = 0; j<n; j++)
		{
			operations and functions;
		}
}

Same process implemented using always a block & a flag

integer i, j, flag;
{ flag = 1; }	// when required
always@(posedge clock)
if(flag)
begin
 if(i == 0 && j == 0)
	begin
 	Outer Loop initialization statements
		operations and functions;
	end
	else if( i == m )
	begin
		flag = 0;	// process completed
	end
	else if( j == n )
	begin 
		j = 0;	// intitialization statements analogous to inner for-loop 
		i = i+1; // updation statement of outer for loop
		operations and functions;
	end
	else
	begin
		operations and functions;
		j = j+1;
	end
end