Add GPU arrival time readback for timing-aware VCD output

.github/workflows/mcu-soc-rebuild.yml

@@ -133,12 +133,22 @@ jobs:
             cp "$LAST_NL" tests/mcu_soc/data/6_final_raw.v
           fi
 
-          # SDF timing (nom corner)
+          # SDF timing — prefer post-PnR (stapostpnr) over pre-PnR (staprepnr)
+          # Use nom_tt (typical) corner for simulation
           if ls "$RUN_DIR"/final/sdf/*.sdf 1>/dev/null 2>&1; then
             cp "$RUN_DIR"/final/sdf/*.sdf tests/mcu_soc/data/6_final.sdf
           else
-            LAST_SDF=$(find "$RUN_DIR" -name '*.sdf' 2>/dev/null | sort -r | head -1)
-            [ -n "$LAST_SDF" ] && cp "$LAST_SDF" tests/mcu_soc/data/6_final.sdf || true
+            POSTPNR_SDF=$(find "$RUN_DIR" -path '*stapostpnr*' -name '*nom_tt*.sdf' 2>/dev/null | head -1)
+            PREPNR_SDF=$(find "$RUN_DIR" -path '*staprepnr*' -name '*nom_tt*.sdf' 2>/dev/null | head -1)
+            if [ -n "$POSTPNR_SDF" ]; then
+              echo "Using post-PnR SDF: $POSTPNR_SDF"
+              cp "$POSTPNR_SDF" tests/mcu_soc/data/6_final.sdf
+            elif [ -n "$PREPNR_SDF" ]; then
+              echo "::warning::Post-PnR SDF not found, using pre-PnR SDF: $PREPNR_SDF"
+              cp "$PREPNR_SDF" tests/mcu_soc/data/6_final.sdf
+            else
+              echo "::warning::No SDF files found"
+            fi
           fi
 
           # SDC constraints

.pdm-python

@@ -0,0 +1 @@
+/Users/roberttaylor/Code/ChipFlow/Loom/.venv/bin/python

CLAUDE.md

@@ -35,10 +35,9 @@ cargo run -r --features hip --bin jacquard -- sim --help
 
 1. **Memory synthesis** (Yosys): Map memories using `memlib_yosys.txt` → outputs `memory_mapped.v`
 2. **Logic synthesis** (DC or Yosys): Synthesize to `aigpdk.lib` cells → outputs `gatelevel.gv`
-3. **Jacquard mapping**: `jacquard map gatelevel.gv result.gemparts`
-4. **Simulation**: `jacquard sim` with `gatelevel.gv result.gemparts input.vcd output.vcd NUM_BLOCKS`
+3. **Simulation**: `jacquard sim gatelevel.gv input.vcd output.vcd NUM_BLOCKS`
 
-Set `NUM_BLOCKS` to 2× the number of GPU streaming multiprocessors (SMs) for CUDA, 2× the number of Compute Units (CUs) for HIP/AMD, or 1 for Metal.
+Partitioning happens automatically at simulation start. Set `NUM_BLOCKS` to 2× the number of GPU streaming multiprocessors (SMs) for CUDA, 2× the number of Compute Units (CUs) for HIP/AMD, or 1 for Metal.
 
 ## Architecture
 
@@ -65,8 +64,7 @@ NetlistDB (Verilog) → AIG → StagedAIG → Partitions → FlattenedScript →
 
 ### Binary Tools (`src/bin/`)
 
-- **`jacquard.rs`**: Unified CLI — `jacquard map` (partition mapping), `jacquard sim` (GPU simulation), `jacquard cosim` (co-simulation)
-- **`timing_sim_cpu.rs`**: CPU-based timing simulation with SDF back-annotation (development tool)
+- **`jacquard.rs`**: Unified CLI — `jacquard sim` (GPU simulation), `jacquard cosim` (co-simulation)
 - **`timing_analysis.rs`**: Static timing analysis utility (development tool)
 
 ### Dependencies (`vendor/eda-infra-rs` submodule)
@@ -118,15 +116,9 @@ cargo run -r --features metal --bin jacquard -- sim ... --max-cycles 1000
 Pre-synthesized benchmark designs are in `benchmarks/dataset/` (git submodule). See `benchmarks/README.md` for full instructions.
 
 ```bash
-# Generate partition file (NVDLA - smallest, good for testing)
-cargo run -r --bin jacquard -- map \
-    benchmarks/dataset/nvdlaAIG.gv \
-    benchmarks/nvdla.gemparts
-
-# Run Metal simulation benchmark
+# Run Metal simulation benchmark (NVDLA - smallest, good for testing)
 cargo run -r --features metal --bin jacquard -- sim \
     benchmarks/dataset/nvdlaAIG.gv \
-    benchmarks/nvdla.gemparts \
     benchmarks/dataset/nvdla.pdp_16x6x16_4x2_split_max_int8_0.vcd \
     benchmarks/nvdla_output.vcd \
     1
@@ -158,7 +150,7 @@ uv run netlist-graph path <netlist.v> "<source>" "<target>"
 # Search for nets matching pattern
 uv run netlist-graph search <netlist.v> "<pattern>"
 
-# Generate watchlist JSON for timing_sim_cpu
+# Generate watchlist JSON for signal monitoring
 uv run netlist-graph watchlist <netlist.v> output.json signal1 signal2 ...
 
 # Interactive mode for exploration
@@ -177,14 +169,3 @@ uv run netlist-graph path tests/timing_test/minimal_build/6_final.v "gpio_in[40]
 ### Timing Violation Detection
 
 See `docs/timing-violations.md` for the full guide on enabling GPU-side setup/hold violation checks, interpreting violation reports, and tracing violations back to source signals using `netlist_graph`.
-
-### Timing Simulation with Signal Tracing
-
-```bash
-# Create watchlist and trace signals
-cargo run -r --bin timing_sim_cpu -- netlist.v \
-  --config testbench.json \
-  --watchlist signals.json \
-  --trace-output trace.csv \
-  --max-cycles 1000
-```

README.md

@@ -59,28 +59,22 @@ cargo build -r --features cuda --bin jacquard
 
 ## Usage
 
-Jacquard operates in two phases:
-
-1. **Map** your synthesized gate-level netlist to a `.gemparts` file (one-time cost):
-
-```sh
-cargo run -r --bin jacquard -- map design.gv design.gemparts
-```
-
-2. **Simulate** with a VCD input waveform:
+Simulate a gate-level netlist with a VCD input waveform:
 
 ```sh
 # Metal (macOS) - use NUM_BLOCKS=1
-cargo run -r --features metal --bin jacquard -- sim design.gv design.gemparts input.vcd output.vcd 1
+cargo run -r --features metal --bin jacquard -- sim design.gv input.vcd output.vcd 1
 
 # CUDA (Linux) - set NUM_BLOCKS to 2x your GPU's SM count
-cargo run -r --features cuda --bin jacquard -- sim design.gv design.gemparts input.vcd output.vcd NUM_BLOCKS
+cargo run -r --features cuda --bin jacquard -- sim design.gv input.vcd output.vcd NUM_BLOCKS
 
 # With SDF timing back-annotation:
-cargo run -r --features metal --bin jacquard -- sim design.gv design.gemparts input.vcd output.vcd 1 \
+cargo run -r --features metal --bin jacquard -- sim design.gv input.vcd output.vcd 1 \
   --sdf design.sdf --sdf-corner typ
 ```
 
+Partitioning (mapping the design to GPU blocks) happens automatically at startup.
+
 **See [docs/usage.md](./docs/usage.md) for full documentation** including synthesis preparation, VCD scope handling, and troubleshooting.
 
 ## Documentation

benchmarks/.gitignore

@@ -1,5 +1,2 @@
-# Generated partition files (can be large, generate locally)
-*.gemparts
-
 # Simulation outputs
 *_output.vcd

benchmarks/README.md

@@ -23,48 +23,27 @@ git submodule update --init --recursive
 
 ## Running Benchmarks
 
-### 1. Generate partition files (one-time)
+### 1. Run Metal simulation
 
-Each design needs a `.gemparts` file generated by the partitioner:
+Partitioning happens automatically at startup.
 
 ```bash
-# NVDLA (smallest, good for testing)
-cargo run -r --features metal --bin cut_map_interactive -- \
+# NVDLA benchmark (smallest, good for testing)
+cargo run -r --features metal --bin jacquard -- sim \
     benchmarks/dataset/nvdlaAIG.gv \
-    benchmarks/nvdla.gemparts
-
-# Rocket
-cargo run -r --features metal --bin cut_map_interactive -- \
-    benchmarks/dataset/rocketAIG.gv \
-    benchmarks/rocket.gemparts
-
-# Gemmini
-cargo run -r --features metal --bin cut_map_interactive -- \
-    benchmarks/dataset/gemminiAIG.gv \
-    benchmarks/gemmini.gemparts
-```
-
-### 2. Run Metal simulation
-
-```bash
-# NVDLA benchmark
-cargo run -r --features metal --bin metal_test -- \
-    benchmarks/dataset/nvdlaAIG.gv \
-    benchmarks/nvdla.gemparts \
     benchmarks/dataset/nvdla.pdp_16x6x16_4x2_split_max_int8_0.vcd \
     benchmarks/nvdla_output.vcd \
     1
 
 # Rocket benchmark
-cargo run -r --features metal --bin metal_test -- \
+cargo run -r --features metal --bin jacquard -- sim \
     benchmarks/dataset/rocketAIG.gv \
-    benchmarks/rocket.gemparts \
     benchmarks/dataset/rocket.median.vcd \
     benchmarks/rocket_output.vcd \
     1
 ```
 
-### 3. Criterion micro-benchmarks
+### 2. Criterion micro-benchmarks
 
 ```bash
 cargo bench --bench event_buffer

csrc/kernel_v1.cu

@@ -24,18 +24,20 @@ void simulate_v1_noninteractive_simple_scan_cuda(
   u32 *sram_xmask,
   usize num_cycles,
   usize state_size,
-  u32 *states_noninteractive
+  u32 *states_noninteractive,
+  int arrival_state_offset
   )
 {
   const u32 *timing_constraints = nullptr;
   EventBuffer *event_buffer = nullptr;
-  void *arg_ptrs[11] = {
+  void *arg_ptrs[12] = {
     (void *)&num_blocks, (void *)&num_major_stages,
     (void *)&blocks_start, (void *)&blocks_data,
     (void *)&sram_data, (void *)&sram_xmask,
     (void *)&num_cycles, (void *)&state_size,
     (void *)&states_noninteractive,
-    (void *)&timing_constraints, (void *)&event_buffer
+    (void *)&timing_constraints, (void *)&event_buffer,
+    (void *)&arrival_state_offset
   };
   checkCudaErrors(cudaLaunchCooperativeKernel(
     (void *)simulate_v1_noninteractive_simple_scan, num_blocks, 256,
@@ -56,16 +58,18 @@ void simulate_v1_noninteractive_timed_cuda(
   usize state_size,
   u32 *states_noninteractive,
   const u32 *timing_constraints,
-  u8 *event_buffer
+  u8 *event_buffer,
+  int arrival_state_offset
   )
 {
-  void *arg_ptrs[11] = {
+  void *arg_ptrs[12] = {
     (void *)&num_blocks, (void *)&num_major_stages,
     (void *)&blocks_start, (void *)&blocks_data,
     (void *)&sram_data, (void *)&sram_xmask,
     (void *)&num_cycles, (void *)&state_size,
     (void *)&states_noninteractive,
-    (void *)&timing_constraints, (void *)&event_buffer
+    (void *)&timing_constraints, (void *)&event_buffer,
+    (void *)&arrival_state_offset
   };
   checkCudaErrors(cudaLaunchCooperativeKernel(
     (void *)simulate_v1_noninteractive_simple_scan, num_blocks, 256,

csrc/kernel_v1.hip.cpp

@@ -41,20 +41,22 @@ void simulate_v1_noninteractive_simple_scan_hip(
   u32 *sram_xmask,
   usize num_cycles,
   usize state_size,
-  u32 *states_noninteractive
+  u32 *states_noninteractive,
+  int arrival_state_offset
   )
 {
   validate_warp_size();
 
   const u32 *timing_constraints = nullptr;
   EventBuffer *event_buffer = nullptr;
-  void *arg_ptrs[11] = {
+  void *arg_ptrs[12] = {
     (void *)&num_blocks, (void *)&num_major_stages,
     (void *)&blocks_start, (void *)&blocks_data,
     (void *)&sram_data, (void *)&sram_xmask,
     (void *)&num_cycles, (void *)&state_size,
     (void *)&states_noninteractive,
-    (void *)&timing_constraints, (void *)&event_buffer
+    (void *)&timing_constraints, (void *)&event_buffer,
+    (void *)&arrival_state_offset
   };
   checkHipErrors(hipLaunchCooperativeKernel(
     (void *)simulate_v1_noninteractive_simple_scan,
@@ -76,18 +78,20 @@ void simulate_v1_noninteractive_timed_hip(
   usize state_size,
   u32 *states_noninteractive,
   const u32 *timing_constraints,
-  u8 *event_buffer
+  u8 *event_buffer,
+  int arrival_state_offset
   )
 {
   validate_warp_size();
 
-  void *arg_ptrs[11] = {
+  void *arg_ptrs[12] = {
     (void *)&num_blocks, (void *)&num_major_stages,
     (void *)&blocks_start, (void *)&blocks_data,
     (void *)&sram_data, (void *)&sram_xmask,
     (void *)&num_cycles, (void *)&state_size,
     (void *)&states_noninteractive,
-    (void *)&timing_constraints, (void *)&event_buffer
+    (void *)&timing_constraints, (void *)&event_buffer,
+    (void *)&arrival_state_offset
   };
   checkHipErrors(hipLaunchCooperativeKernel(
     (void *)simulate_v1_noninteractive_simple_scan,