Update 6_final.v with PnR-produced netlist (includes output/clock buffers)

[robtaylor]

Summary

• Cherry-picks the PnR netlist rebuild from PR Update MCU SoC post-P&R test data #44 (6f2a2bd)
• Replaces the local_synth.py-generated 6_final.v with the full post-PnR netlist from librelane
• New netlist includes ~8,000 PnR-inserted cells: 2,247 clock buffer refs, 40 output buffers, fanout buffers
• This closes the structural mismatch between 6_final.v and 6_final.sdf that caused systematic ~242ps timing offsets in the CVC vs Jacquard comparison

Context

The previous 6_final.v was from Yosys synthesis only (31K cells). The SDF from OpenROAD PnR had 39K cells. CVC simulated with full SDF (including output buffer delays), while Jacquard only saw cells in the netlist. This caused a consistent timing gap.

Supersedes #44 (which bundled duplicate code changes from timing-vcd-readback).

Test plan

• CI passes (mcu-soc-metal cosim with the new netlist)
• Verify Jacquard can parse the larger netlist without mapping failures