Fix 2x clock frequency bug and add timing investigation tools

[robtaylor]

Summary

• Fix 2x clock frequency bug in multi-clock scheduler — DFFs only captured every other cycle because the scheduler's per-GCD-tick entries (half-cycle) were consumed one-per-tick instead of paired. This was the root cause of Issue Investigate 2x UART baud rate factor in Amaranth-generated designs #54 (2x UART baud rate, 2x flash clock frequency).
• Add --timing-vcd to cosim for native timing-accurate VCD output with per-signal arrival offsets from SDF data
• Add --dump-dff to cosim for debugging internal DFF state per cycle
• Fix SDF loading for hierarchical netlists: detect and strip instance prefix
• Remove legacy single-clock code path — multi-clock scheduler now handles all cases
• Add SDF timing path tracer (scripts/sdf_trace.py) for debugging timing discrepancies
• Add dump-paths CLI subcommand for AIG critical path analysis
• Wire arrival_state_offset through CUDA/HIP kernels for cross-platform --timing-vcd

Key fix: 2x clock frequency (Issue #54)

The MultiClockScheduler produces one entry per GCD tick (half-cycle). For a single 40ns clock: [falling, rising]. Each cosim tick used ONE entry for both fall and rise phases:

• Even ticks → posedge_flag=0 → DFFs don't capture
• Odd ticks → posedge_flag=1 → DFFs capture

Fix: pair consecutive schedule entries so each tick gets correct fall + rise ops.

Metric	Before	After
flash_clk transitions	485 vs 973 (0.50x)	972 vs 973 (1.00x)
Non-flash GPIO match vs CVC	42.9%	100%

Fixes #54

Test plan

• Cosim MCU SoC passes (SIMULATION: PASSED)
• Non-flash GPIO bits match CVC 100% (was 42.9%)
• Flash clock transition count matches CVC (972 vs 973)
• DFF state dump shows captures every cycle (no frozen pairs)
• CI check (CUDA/HIP builds)