Added pre condition in the verilog module #620
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WalkthroughThe Verilog module code for the T flip-flop in Changes
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Assessment against linked issues: Out-of-scope changesNo out-of-scope changes were found. Warning There were issues while running some tools. Please review the errors and either fix the tool's configuration or disable the tool if it's a critical failure. 🔧 ESLint
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🧹 Nitpick comments (1)
src/simulator/src/sequential/TflipFlop.js (1)
154-160: Good alignment with simulation logic, consider multi-bit syntax improvement.The conditional preset logic correctly aligns the Verilog behavior with the JavaScript simulation logic (lines 72-74), where reset uses
this.preset.value || 0. This change successfully addresses the PR objective of adding precondition logic.For better multi-bit signal handling, consider using width-specific syntax:
- if (pre == 'bx) begin - q <= 'b0; - q_inv <= 'b1; + if (pre === {WIDTH{1'bx}}) begin + q <= {WIDTH{1'b0}}; + q_inv <= {WIDTH{1'b1}}; end else begin q <= pre; q_inv <= ~pre; endHowever, since the original code used
'b0and'b1, maintaining consistency with the existing style is also reasonable.
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src/simulator/src/sequential/TflipFlop.js(1 hunks)
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🧠 Learnings (2)
📓 Common learnings
Learnt from: 092vk
PR: CircuitVerse/cv-frontend-vue#591
File: v1/src/simulator/src/sequential/JKflipFlop.js:159-188
Timestamp: 2025-06-10T11:26:38.102Z
Learning: In the CircuitVerse project, Verilog modules for circuit elements like JKflipFlop are designed to be consistent with the circuit simulation design, which means reset and preset signals are implemented synchronously (triggered on clock edge) rather than asynchronously, even when the signals are named as asynchronous reset/preset.
src/simulator/src/sequential/TflipFlop.js (1)
Learnt from: 092vk
PR: CircuitVerse/cv-frontend-vue#591
File: v1/src/simulator/src/sequential/JKflipFlop.js:159-188
Timestamp: 2025-06-10T11:26:38.102Z
Learning: In the CircuitVerse project, Verilog modules for circuit elements like JKflipFlop are designed to be consistent with the circuit simulation design, which means reset and preset signals are implemented synchronously (triggered on clock edge) rather than asynchronously, even when the signals are named as asynchronous reset/preset.
Fixes #561
Describe the changes you have made in this PR -
Note: Please check Allow edits from maintainers. if you would like us to assist in the PR.
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