Skip to content

Workaround in Zynq port for missing macros when using SDT drivers #1247

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 10 commits into from
May 15, 2025

Conversation

mike919192
Copy link
Contributor

Workaround in Zynq port for missing macros when using SDT drivers

Description

This is a followup to PR #1227 . This is also discussed in the FreeRTOS forums

The summary of the problem is that with the new SDT drivers, Xilinx removed macros that were previously used as clock divider values for various link speeds (XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 and similar). It seems that the intention is that the macros are no longer necessary, except that some link speeds do not function without writing the macro values to the SLCR_GEM0_CLK_CTRL_ADDR register. For me 1000Mbps worked without writing to the register but 100Mbps does not work. I have also reproduced the same problem with the Xilinx lwip port, so the problem is definitely with these missing macros.

The best work around seems to be to define these missing macros in the FreeRTOSIPConfig.h for the time being. The PR changes the section of the that writes the macro values to the register. It will now write the values if the macros exist, otherwise it will not perform a write.

Test Steps

I have again tested that this code works with both the old and new Xilinx drivers. I have also tested both the old and new drivers at 1000Mbps and 100Mbps link speeds.

Checklist:

Like before the changes are limited to the portable layer, which I don't believe have any unit tests.

  • I have tested my changes. No regression in existing tests.
  • I have modified and/or added unit-tests to cover the code changes in this Pull Request.

Related Issue

By submitting this pull request, I confirm that you can use, modify, copy, and redistribute this contribution, under the terms of your choice.

@mike919192 mike919192 requested a review from a team as a code owner May 2, 2025 12:55
@tony-josi-aws
Copy link
Member

@mike919192

Thanks for creating this follow-up PR and contributing to FreeRTOS+TCP.

@bhoomrs bhoomrs requested a review from tony-josi-aws May 7, 2025 07:22
@bhoomrs bhoomrs merged commit 405ab5f into FreeRTOS:main May 15, 2025
10 checks passed
@mike919192
Copy link
Contributor Author

mike919192 commented May 15, 2025

@tony-josi-aws Thanks for merging this. I think that both this PR and the also #1227 probably also apply to the xilinx ultrascale port. I think I have access to the right hardware to run the ultrascale port, but I haven't had any time to check how close the code is to the Zynq port. Either way this probably should be a todo item, to check if ultrascale also needs updated and test it.

@tony-josi-aws
Copy link
Member

@mike919192

Thank you. Yes, it should be a to-do item. I believe these 2 PRs should help someone trying to upgrade the ultrascale port to the latest drivers as a reference.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

4 participants