HPipe

Hamster's Pipelined RISC-V CPU Core (RV32IMC)

This design is for learning purpose

Quick Start

Export to SystemVerilog

make verilog

Run specific App with HPipe simulator

make sim APP=rv-tests    # Folder names in `sim/app`, except `common`, are valid app names
make wave APP=rv-tests   # With waveform generated under `sim/app/build/<name>/<name>.fst`

Run with a GDB session

make gdb-server

# In another shell
make gdb APP=rv-tests

Run Backend Analysis:

Use vivado to run a FPGA synthesis and get reports

make init-fpga # This only need to run once
make fpga

Use yosys-based tools to run a ASIC synthesis and get reports

make init-asic # This only need to run once
               # Might require a really long time as PDK will be downloaded
make asic

Architecture

This Core implements a 6-stage pipelined CPU.

Currently it supports RV32IMC_izcsr, but more extensions are on the way.

IF & BTB

The IF stage involves a mixture of branch prediction modules:

• TargetBuffer: A address cache that stores branch target, adopting a 2-way group assosiation
• HistTable: 2-bit saturation counters for prediction of b-class instructions (beq, bne, etc.)
• RetAddrStack: A LIFO stack that pushes and pops function exits

The Penalty of branch miss is 3 cycles.

ID

The ID stage decodes each instruction into uops that determines the behavour of EX and MEM stages.

SG

The SG stage differs HPipe from classical 5-stage CPUs.

SG is short of "Source Generation", at which stage would the oprands for EX and MEM stages be generated through either reading RegFile, CsrFile or receiving from Feed-Forwards.

This stage is introduced as timing is not sufficient for Decoder and Source Generation to work in the same stage.

EX

The EX stage currently uses Carry Lookahead Adder, Radix-4 Booth Multiplier and Non-restoring remainder Divider as its arithmatic implemention

• The Carry Lookahead Adder implements a group-of-4 hierarchy, i.e. at most 4 adders shares a Carry Lookahead Unit
• The Radix-4 Booth Multiplier currently produces result in 1 cycle, which might have impact on frequency
• The Non-restoring remainder Divider requires 32 cycles for a normal divide operation

Note that DSP Macros are used when specified Fpga = true in parameters

MEM

The MEM stage uses a simple interface to interact with MMIOs. AXI support is planned.

WB

The WB stage signals whether a valid instruction is retired.

Feed Forward

There're 2 primary paths to forward:

1. SG

The SG stage requires up-to-date source data (rs1 & rs2). Thus, if rs1 or rs2 will be written by the instructions executing in EX or MEM stage, the dest data should be forwarded to SG.

• EX -> SG: No stalls/bubbles required
• MEM -> SG: No stalls/bubbles required
• EX(needs MEM) -> SG: 1 cycle's stall

2. IF

The IF stage requires rs1 to generate the address of JALR to predict jump location.

If rs1 can be forwarded, BTB will predict correctly, as JALR always takes branch; otherwise, BTB won't predict, as dest pc is not known for now.

• ID -> IF: Will not predict
• SG -> IF: Will not predict
• EX -> IF: Will not predict (Even though it can, this is for performance consideration)
• MEM -> IF: Predict

PPA

FPGA

Characteristics were estimated using Xilinx part xc7a200t

• Power = 433mW
• Clock Freq = 169.5MHz
• Utilization
  • LUT = 4705
  • FF = 5030
  • DSP = 4

ASIC

Characteristics were estimated using icsprout55 55nm PDK

• Power = 35.072mW
• Clock Freq = 196.1MHz
• Area = 77822.08um2

The mass decline of Frequency comes from the io preservation by OpenSTA

Road Map

• Enable GDB Debugging
• Testbenches & Unit Tests using verilator and riscv-tests
• RV32M extension
• Yosys-based backend analysis
• Branch Prediction & Optimized Branch Penalty
• CSRs supporting M mode
• RV32C extension
• PLIC & CLINT
• Zephyr OS
• L1 Cache & TLB
• AXI Bus
• Coremark Bench

ScreenShots

1. HPipe under simulation, passing every isa test in riscv-tests

2. Waveform of a running HPipe

3. Coremark result ran by HPipe

Acknowledgements

This project exists with the help of the Open Source Community.

Thanks

• The YSYX Project for providing a comprehensive walkthough of the Processor full-stack design & validation, along with a set of open source projects. The transplant of riscv-tests and backend won't exist without it.
• mini-gdbstub for providing a really simple gdb server framework