RV64 Multi-Cycle CPU

A modular 64-bit RISC-V CPU and SoC implemented in SystemVerilog.

Features a multi-cycle microarchitecture, RV64I base integer support, the RV64M multiply/divide extension, machine-mode CSRs, and synchronous trap handling.

The design is simulated with Verilator, supporting both directed assembly regressions and self-checking bare-metal C programs.

Features

• RV64I base ISA
• RV64M multiply/divide extension
• Zicsr CSR instructions
• Zifencei FENCE.I instruction
• Multi-cycle CPU architecture
• 32 x 64-bit integer register file
• Unified instruction/data bus
• Byte, halfword, word, and doubleword memory access
• Machine-mode CSR file
• Synchronous exception and trap handling
• MRET trap return
• Bare-metal C execution
• Cycle-accurate RAM model
• Verilator simulation with VCD waveform output
• Self-checking assembly and C tests
• Automated assembly regression suite
• GitHub Actions CI

Requirements

Required tools:

• Verilator
• RISC-V GCC toolchain
• make
• g++
• GTKWave (optional)

Running the Simulation

From the project root:

• Run full assembly regression:
  • make asm
• Run bare-metal C self-test:
  • make c
• Clean build outputs:
  • make clean

Use gtkwave sim/dump.vcd to view waveforms.

Current ISA Support

ALU + MULDIV (M Extension)

Registers

ADD SUB AND OR XOR
SLL SRL SRA
SLT SLTU
MUL MULH MULHU MULHSU
DIV DIVU REM REMU

Immediates

ADDI ANDI ORI XORI
SLTI SLTIU
SLLI SRLI SRAI

RV64 W-Instructions

ADDIW
ADDW SUBW
SLLIW SRLIW SRAIW
SLLW SRLW SRAW
MULW
DIVW DIVUW REMW REMUW

Upper Immediates

LUI AUIPC

Loads / Stores

LB LBU LH LHU LW LWU LD
SB SH SW SD

Control Flow

JAL JALR
BEQ BNE
BLT BGE
BLTU BGEU

CSR Instructions

CSRRW CSRRS CSRRC
CSRRWI CSRRSI CSRRCI

Implemented machine-mode CSRs:

mstatus mtvec mscratch mepc mcause mtval

System

EBREAK
ECALL
MRET

Treated as legal NOPs:

FENCE
FENCE.I

Exception / Trap Support

Implemented synchronous exceptions:

• Instruction address misaligned
• Instruction access fault
• Illegal instruction
• Breakpoint
• Load address misaligned
• Load access fault
• Store address misaligned
• Store access fault
• Environment call from M-mode

Trap entry saves:

• Faulting PC to mepc
• Cause to mcause
• Fault information to mtval

and redirects execution to mtvec.

MRET returns execution to mepc.

Current privileged support is machine mode only. Interrupts are not implemented.

Testing

Assembly regression includes:

• rv64_test.S
• csr_test.S
• trap_test.S
• invalid_csr_test.S
• mstatus_test.S

The simulator automatically detects PASS and FAIL addresses and exits with the corresponding status.

Run all assembly tests with:

make asm

Run the bare-metal C self-test with:

make c

Milestones

See docs/ for detailed descriptions.

• Milestone 0: Project setup
• Milestone 1: Smoke simulation
• Milestone 2: SoC + RAM
• Milestone 3: Multi-cycle CPU skeleton
• Milestone 4: RV64I implementation
• Milestone 5: Run bare-metal C
• Milestone 6: M Extension
• Milestone 7: CSRs + Traps

Design Overview

The CPU uses a multi-cycle architecture controlled by a central FSM.

Main flow:

IFETCH -> DECODE -> MEM / EXEC -> IFETCH

Exceptions redirect through a trap state:

EXCEPTION -> TRAP -> mtvec

The design uses a single unified bus for instruction fetch and memory operations.

Main RTL modules include:

• frontend.sv
• decoder.sv
• regfile.sv
• alu.sv
• muldiv.sv
• exu.sv
• lsu.sv
• csr_file.sv
• control_fsm.sv
• soc.sv
• ram.sv

Memory

RAM base / reset PC:

0x0000000080000000

Current simulated RAM size:

1 MiB