Test Status

This page summarises what has been tested, and what currently works, what testing is needed, in Visual2. Please update it as this changes.

The Test DSL is in another project and well sorted out now. It allows very quick generation of new random tests using VisUAL as a model to generate results against which Visual2 can be tested. The test data takes some time to generate (due to Visual) but is written to test files. These can be moved to Visual2 and run making testing Visual2 very fast. Current tests take a few seconds to run under Visual2. Complete longer testing will not take more than a few minutes.

Because testing is checking emulator status against Visual not all tests pass. There are some corner issues in the spec where a different functionality from Visual is better in the DP instructions. Also there are some issues about which instructions have specific registers disallowed that vary between architectures. This is dealt with now by constructing tests that avoid these registers, or by allowing Visual2 to return valid results when Visual errors.

Status Summary

Date	DP	LDR STR	LDM STM	PC read write	MISC	Cond branch	BL
24/4/18	Passes longer tests needed	Passes	Passes	Fails	tests needed	Passes	tests needed
28/4/18	Passes longer tests needed	Passes	Passes	Passes	Passes more tests needed	Passes	Passes

DP Module

Although all modes etc are tested, not all are tested under all conditions. we need a long test which will take a few hours to generate and a few minutes to test. Probably we should alter framework to allow either quick tests or long tests run from GUI, since manually changing test files is not nice.

PC Read/Write

All works, see computed branch tests.

MISC

All of these instructions have been tested minimally, they need proper testing. Basic tests have been done for DCD, LDR =, ADR, DCD, DCB, FILL

Other

It would be worthwhile constructing a random integration test generator that put together N non-branch instructions for testing