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Add support for `celldefine, vpiCellInstance
This patch adds real functionality for `celldefine and pushes this property to the run time which can access this with vpiCellInstance. This is technically only available for a module, but all scopes have the property and only modules should return true when the 'endmodule' is between a `celldefine and `endcelldefine directive.
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,5 +1,5 @@ | ||
/* | ||
* Copyright (c) 1998-2008 Stephen Williams ([email protected]) | ||
* Copyright (c) 1998-2009 Stephen Williams ([email protected]) | ||
* | ||
* This source code is free software; you can redistribute it | ||
* and/or modify it in source code form under the terms of the GNU | ||
|
@@ -29,6 +29,7 @@ Module::Module(perm_string n) | |
: PScope(n) | ||
{ | ||
library_flag = false; | ||
is_cell = false; | ||
default_nettype = NetNet::NONE; | ||
} | ||
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||
|
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,7 +1,7 @@ | ||
#ifndef __parse_misc_H | ||
#define __parse_misc_H | ||
/* | ||
* Copyright (c) 1998-2000 Stephen Williams ([email protected]) | ||
* Copyright (c) 1998-2009 Stephen Williams ([email protected]) | ||
* | ||
* This source code is free software; you can redistribute it | ||
* and/or modify it in source code form under the terms of the GNU | ||
|
@@ -65,4 +65,6 @@ extern ostream& operator << (ostream&, const YYLTYPE&loc); | |
extern unsigned error_count, warn_count; | ||
extern unsigned long based_size; | ||
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extern bool in_celldefine; | ||
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#endif |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,5 +1,5 @@ | ||
/* | ||
* Copyright (c) 1998-2008 Stephen Williams ([email protected]) | ||
* Copyright (c) 1998-2009 Stephen Williams ([email protected]) | ||
* | ||
* This source code is free software; you can redistribute it | ||
* and/or modify it in source code form under the terms of the GNU | ||
|
@@ -1147,7 +1147,9 @@ void Module::dump(ostream&out) const | |
out << " *) "; | ||
} | ||
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out << "module " << mod_name() << ";" << endl; | ||
out << "module " << mod_name() << ";"; | ||
if (is_cell) out << " // Is in `celldefine."; | ||
out << endl; | ||
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||
for (unsigned idx = 0 ; idx < ports.size() ; idx += 1) { | ||
port_t*cur = ports[idx]; | ||
|
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