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Support timescales in design units that aren't inside a module.
SystemVerilog allows tasks, functions, and classes to be defined at the root level or inside packages, so we can't rely on an enclosing module being present to provide the timescale.
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Original file line number | Diff line number | Diff line change |
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@@ -1,5 +1,5 @@ | ||
/* | ||
* Copyright (c) 1998-2015 Stephen Williams ([email protected]) | ||
* Copyright (c) 1998-2016 Stephen Williams ([email protected]) | ||
* | ||
* This source code is free software; you can redistribute it | ||
* and/or modify it in source code form under the terms of the GNU | ||
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@@ -36,9 +36,6 @@ Module::Module(LexicalScope*parent, perm_string n) | |
program_block = false; | ||
uc_drive = UCD_NONE; | ||
timescale_warn_done = false; | ||
time_unit = 0; | ||
time_precision = 0; | ||
time_from_timescale = false; | ||
} | ||
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Module::~Module() | ||
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Original file line number | Diff line number | Diff line change |
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@@ -1,7 +1,7 @@ | ||
#ifndef IVL_Module_H | ||
#define IVL_Module_H | ||
/* | ||
* Copyright (c) 1998-2015 Stephen Williams ([email protected]) | ||
* Copyright (c) 1998-2016 Stephen Williams ([email protected]) | ||
* | ||
* This source code is free software; you can redistribute it | ||
* and/or modify it in source code form under the terms of the GNU | ||
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@@ -121,10 +121,6 @@ class Module : public PScopeExtra, public LineInfo { | |
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map<perm_string,PExpr*> attributes; | ||
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/* These are the timescale for this module. The default is | ||
set by the `timescale directive. */ | ||
int time_unit, time_precision; | ||
bool time_from_timescale; | ||
bool timescale_warn_done; | ||
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/* The module has a list of generate schemes that appear in | ||
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,5 +1,5 @@ | ||
/* | ||
* Copyright (c) 2008,2010 Stephen Williams ([email protected]) | ||
* Copyright (c) 2008,2016 Stephen Williams ([email protected]) | ||
* | ||
* This source code is free software; you can redistribute it | ||
* and/or modify it in source code form under the terms of the GNU | ||
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@@ -24,14 +24,21 @@ bool LexicalScope::var_init_needs_explicit_lifetime() const | |
return false; | ||
} | ||
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PScope::PScope(perm_string n, LexicalScope*parent) | ||
: LexicalScope(parent), name_(n) | ||
PWire* LexicalScope::wires_find(perm_string name) | ||
{ | ||
map<perm_string,PWire*>::const_iterator cur = wires.find(name); | ||
if (cur == wires.end()) | ||
return 0; | ||
else | ||
return (*cur).second; | ||
} | ||
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PScope::PScope(perm_string n) | ||
: LexicalScope(0), name_(n) | ||
PScope::PScope(perm_string n, LexicalScope*parent) | ||
: LexicalScope(parent), name_(n) | ||
{ | ||
time_unit = 0; | ||
time_precision = 0; | ||
time_from_timescale = false; | ||
} | ||
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PScope::~PScope() | ||
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@@ -41,25 +48,11 @@ PScope::~PScope() | |
delete it->second; | ||
} | ||
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PWire* LexicalScope::wires_find(perm_string name) | ||
{ | ||
map<perm_string,PWire*>::const_iterator cur = wires.find(name); | ||
if (cur == wires.end()) | ||
return 0; | ||
else | ||
return (*cur).second; | ||
} | ||
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PScopeExtra::PScopeExtra(perm_string n, LexicalScope*parent) | ||
: PScope(n, parent) | ||
{ | ||
} | ||
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PScopeExtra::PScopeExtra(perm_string n) | ||
: PScope(n) | ||
{ | ||
} | ||
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PScopeExtra::~PScopeExtra() | ||
{ | ||
} |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,5 +1,5 @@ | ||
/* | ||
* Copyright (c) 2000-2015 Stephen Williams ([email protected]) | ||
* Copyright (c) 2000-2016 Stephen Williams ([email protected]) | ||
* Copyright CERN 2013 / Stephen Williams ([email protected]) | ||
* | ||
* This source code is free software; you can redistribute it | ||
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@@ -54,6 +54,15 @@ | |
# include <cassert> | ||
# include "ivl_assert.h" | ||
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void set_scope_timescale(Design*des, NetScope*scope, PScope*pscope) | ||
{ | ||
scope->time_unit(pscope->time_unit); | ||
scope->time_precision(pscope->time_precision); | ||
scope->time_from_timescale(pscope->time_from_timescale); | ||
des->set_precision(pscope->time_precision); | ||
} | ||
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typedef map<perm_string,LexicalScope::param_expr_t>::const_iterator mparm_it_t; | ||
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static void collect_parm_item_(Design*des, NetScope*scope, perm_string name, | ||
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@@ -523,6 +532,7 @@ static void elaborate_scope_class(Design*des, NetScope*scope, PClass*pclass) | |
class_scope->set_class_def(use_class); | ||
use_class->set_class_scope(class_scope); | ||
use_class->set_definition_scope(scope); | ||
set_scope_timescale(des, class_scope, pclass); | ||
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// Collect the properties, elaborate them, and add them to the | ||
// elaborated class definition. | ||
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@@ -654,8 +664,10 @@ static void elaborate_scope_task(Design*des, NetScope*scope, PTask*task) | |
task_scope->is_auto(task->is_auto()); | ||
task_scope->set_line(task); | ||
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if (scope==0) | ||
if (scope==0) { | ||
set_scope_timescale(des, task_scope, task); | ||
des->add_root_task(task_scope, task); | ||
} | ||
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if (debug_scopes) { | ||
cerr << task->get_fileline() << ": elaborate_scope_task: " | ||
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@@ -719,8 +731,10 @@ static void elaborate_scope_func(Design*des, NetScope*scope, PFunction*task) | |
task_scope->is_auto(task->is_auto()); | ||
task_scope->set_line(task); | ||
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if (scope==0) | ||
if (scope==0) { | ||
set_scope_timescale(des, task_scope, task); | ||
des->add_root_task(task_scope, task); | ||
} | ||
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if (debug_scopes) { | ||
cerr << task->get_fileline() << ": elaborate_scope_func: " | ||
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@@ -1750,11 +1764,7 @@ void PGModule::elaborate_scope_mod_instances_(Design*des, Module*mod, NetScope*s | |
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instances[idx] = my_scope; | ||
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// Set time units and precision. | ||
my_scope->time_unit(mod->time_unit); | ||
my_scope->time_precision(mod->time_precision); | ||
my_scope->time_from_timescale(mod->time_from_timescale); | ||
des->set_precision(mod->time_precision); | ||
set_scope_timescale(des, my_scope, mod); | ||
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// Look for module parameter replacements. The "replace" map | ||
// maps parameter name to replacement expression that is | ||
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,5 +1,5 @@ | ||
/* | ||
* Copyright (c) 2003-2011 Stephen Williams ([email protected]) | ||
* Copyright (c) 2003-2016 Stephen Williams ([email protected]) | ||
* | ||
* This source code is free software; you can redistribute it | ||
* and/or modify it in source code form under the terms of the GNU | ||
|
@@ -229,15 +229,18 @@ unsigned is_string_obj(vpiHandle obj) | |
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/* | ||
* Find the enclosing module. | ||
* Find the enclosing module. If there is no enclosing module (which can be | ||
* the case in SystemVerilog), return the highest enclosing scope. | ||
*/ | ||
vpiHandle sys_func_module(vpiHandle obj) | ||
{ | ||
assert(obj); | ||
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while (vpi_get(vpiType, obj) != vpiModule) { | ||
obj = vpi_handle(vpiScope, obj); | ||
assert(obj); | ||
vpiHandle scope = vpi_handle(vpiScope, obj); | ||
if (scope == 0) | ||
break; | ||
obj = scope; | ||
} | ||
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return obj; | ||
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