Rework handling of lexical scope

Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
Josephtek · Feb 25, 2008 · 8e704cb · 8e704cb
1 parent b0e4a68
commit 8e704cb
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Showing 18 changed files with 553 additions and 583 deletions.
diff --git a/Module.cc b/Module.cc
@@ -54,16 +54,6 @@ void Module::add_function(perm_string name, PFunction *func)
       funcs_[name] = func;
 }
 
-PWire* Module::add_wire(PWire*wire)
-{
-      PWire*&ep = wires_[wire->path()];
-      if (ep) return ep;
-
-      assert(ep == 0);
-      ep = wire;
-      return wire;
-}
-
 void Module::add_behavior(PProcess*b)
 {
       behaviors_.push_back(b);
@@ -111,15 +101,6 @@ unsigned Module::find_port(const char*name) const
 }
 
 
-PWire* Module::get_wire(const pform_name_t&name) const
-{
-      map<pform_name_t,PWire*>::const_iterator obj = wires_.find(name);
-      if (obj == wires_.end())
-	    return 0;
-      else
-	    return (*obj).second;
-}
-
 PGate* Module::get_gate(perm_string name)
 {
       for (list<PGate*>::iterator cur = gates_.begin()

diff --git a/Module.h b/Module.h
@@ -1,7 +1,7 @@
 #ifndef __Module_H
 #define __Module_H
 /*
- * Copyright (c) 1998-2004 Stephen Williams ([email protected])
+ * Copyright (c) 1998-2008 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -18,9 +18,7 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#ifdef HAVE_CVS_IDENT
-#ident "$Id: Module.h,v 1.43 2007/05/24 04:07:11 steve Exp $"
-#endif
+
 
 # include  <list>
 # include  <map>
@@ -133,12 +131,6 @@ class Module : public PScope, public LineInfo {
       perm_string mod_name() const { return pscope_name(); }
 
       void add_gate(PGate*gate);
-
-	// The add_wire method adds a wire by name, but only if the
-	// wire name doesn't already exist. Either way, the result is
-	// the existing wire or the pointer passed in.
-      PWire* add_wire(PWire*wire);
-
       void add_behavior(PProcess*behave);
       void add_task(perm_string name, PTask*def);
       void add_function(perm_string name, PFunction*def);
@@ -147,9 +139,6 @@ class Module : public PScope, public LineInfo {
       const svector<PEIdent*>& get_port(unsigned idx) const;
       unsigned find_port(const char*name) const;
 
-	// Find a wire by name. This is used for connecting gates to
-	// existing wires, etc.
-      PWire* get_wire(const pform_name_t&name) const;
       PGate* get_gate(perm_string name);
 
       const list<PGate*>& get_gates() const;
@@ -164,7 +153,6 @@ class Module : public PScope, public LineInfo {
       bool elaborate_sig(Design*, NetScope*scope) const;
 
     private:
-      map<pform_name_t,PWire*> wires_;
       list<PGate*> gates_;
       list<PProcess*> behaviors_;
       map<perm_string,PTask*> tasks_;
@@ -178,26 +166,4 @@ class Module : public PScope, public LineInfo {
       Module& operator= (const Module&);
 };
 
-
-/*
- * $Log: Module.h,v $
- * Revision 1.43  2007/05/24 04:07:11  steve
- *  Rework the heirarchical identifier parse syntax and pform
- *  to handle more general combinations of heirarch and bit selects.
- *
- * Revision 1.42  2007/04/19 02:52:53  steve
- *  Add support for -v flag in command file.
- *
- * Revision 1.41  2006/09/23 04:57:19  steve
- *  Basic support for specify timing.
- *
- * Revision 1.40  2006/04/10 00:37:42  steve
- *  Add support for generate loops w/ wires and gates.
- *
- * Revision 1.39  2006/03/30 01:49:07  steve
- *  Fix instance arrays indexed by overridden parameters.
- *
- * Revision 1.38  2005/07/11 16:56:50  steve
- *  Remove NetVariable and ivl_variable_t structures.
- */
 #endif
diff --git a/PGenerate.cc b/PGenerate.cc
@@ -33,19 +33,9 @@ PGenerate::~PGenerate()
 {
 }
 
-PWire* PGenerate::add_wire(PWire*wire)
+PWire* PGenerate::get_wire(perm_string name) const
 {
-      PWire*&ep = wires[wire->path()];
-      if (ep) return ep;
-
-      assert(ep == 0);
-      ep = wire;
-      return wire;
-}
-
-PWire* PGenerate::get_wire(const pform_name_t&name) const
-{
-      map<pform_name_t,PWire*>::const_iterator obj = wires.find(name);
+      map<perm_string,PWire*>::const_iterator obj = wires.find(name);
       if (obj == wires.end())
 	    return 0;
       else

diff --git a/PGenerate.h b/PGenerate.h
@@ -71,9 +71,8 @@ class PGenerate : public LineInfo {
       PExpr*loop_test;
       PExpr*loop_step;
 
-      map<pform_name_t,PWire*>wires;
-      PWire* add_wire(PWire*);
-      PWire* get_wire(const pform_name_t&name) const;
+      map<perm_string,PWire*>wires;
+      PWire* get_wire(perm_string name) const;
 
       list<PGate*> gates;
       void add_gate(PGate*);

diff --git a/PScope.cc b/PScope.cc
@@ -27,3 +27,12 @@ PScope::PScope(perm_string n, PScope*p)
 PScope::~PScope()
 {
 }
+
+PWire* PScope::wires_find(perm_string name)
+{
+      map<perm_string,PWire*>::const_iterator cur = wires.find(name);
+      if (cur == wires.end())
+	    return 0;
+      else
+	    return (*cur).second;
+}
diff --git a/PScope.h b/PScope.h
@@ -24,6 +24,10 @@
 # include  <map>
 
 class PEvent;
+class PWire;
+
+class Design;
+class NetScope;
 
 /*
  * The PScope class is a base representation of an object that
@@ -50,9 +54,18 @@ class PScope {
       perm_string pscope_name() const { return name_; }
       PScope* pscope_parent() { return parent_; }
 
+	// Nets an variables (wires) in the scope
+      map<perm_string,PWire*>wires;
+      PWire* wires_find(perm_string name);
+
 	// Named events in the scope.
       map<perm_string,PEvent*>events;
 
+    protected:
+      void dump_wires_(ostream&out, unsigned indent) const;
+
+      bool elaborate_sig_wires_(Design*des, NetScope*scope) const;
+
     private:
       perm_string name_;
       PScope*parent_;

diff --git a/PWire.cc b/PWire.cc
@@ -22,11 +22,11 @@
 # include  "PExpr.h"
 # include  <assert.h>
 
-PWire::PWire(const pform_name_t&n,
+PWire::PWire(perm_string n,
 	     NetNet::Type t,
 	     NetNet::PortType pt,
 	     ivl_variable_type_t dt)
-: hname_(n), type_(t), port_type_(pt), data_type_(dt),
+: name_(n), type_(t), port_type_(pt), data_type_(dt),
   signed_(false), isint_(false),
   port_msb_(0), port_lsb_(0), port_set_(false),
   net_msb_(0), net_lsb_(0), net_set_(false), error_cnt_(0),
@@ -44,9 +44,9 @@ NetNet::Type PWire::get_wire_type() const
       return type_;
 }
 
-const pform_name_t& PWire::path() const
+perm_string PWire::basename() const
 {
-      return hname_;
+      return name_;
 }
 
 bool PWire::set_wire_type(NetNet::Type t)
@@ -153,7 +153,7 @@ void PWire::set_range(PExpr*m, PExpr*l, PWSRType type)
       switch (type) {
 	  case SR_PORT:
 	    if (port_set_) {
-		  cerr << get_fileline() << ": error: Port ``" << hname_
+		  cerr << get_fileline() << ": error: Port ``" << name_
 		       << "'' has already been declared a port." << endl;
 		  error_cnt_ += 1;
 	    } else {
@@ -165,7 +165,7 @@ void PWire::set_range(PExpr*m, PExpr*l, PWSRType type)
 
 	  case SR_NET:
 	    if (net_set_) {
-		  cerr << get_fileline() << ": error: Net ``" << hname_
+		  cerr << get_fileline() << ": error: Net ``" << name_
 		       << "'' has already been declared." << endl;
 		  error_cnt_ += 1;
 	    } else {
@@ -178,12 +178,12 @@ void PWire::set_range(PExpr*m, PExpr*l, PWSRType type)
 	  case SR_BOTH:
 	    if (port_set_ || net_set_) {
 		  if (port_set_) {
-		        cerr << get_fileline() << ": error: Port ``" << hname_
+		        cerr << get_fileline() << ": error: Port ``" << name_
 		             << "'' has already been declared a port." << endl;
 		        error_cnt_ += 1;
 		  }
 		  if (net_set_) {
-		        cerr << get_fileline() << ": error: Net ``" << hname_
+		        cerr << get_fileline() << ": error: Net ``" << name_
 		             << "'' has already been declared." << endl;
 		        error_cnt_ += 1;
 		  }
@@ -202,7 +202,7 @@ void PWire::set_range(PExpr*m, PExpr*l, PWSRType type)
 void PWire::set_memory_idx(PExpr*ldx, PExpr*rdx)
 {
       if (lidx_ != 0 || ridx_ != 0) {
-	    cerr << get_fileline() << ": error: Array ``" << hname_
+	    cerr << get_fileline() << ": error: Array ``" << name_
 	         << "'' has already been declared." << endl;
 	    error_cnt_ += 1;
       } else {

diff --git a/PWire.h b/PWire.h
@@ -56,13 +56,13 @@ enum PWSRType {SR_PORT, SR_NET, SR_BOTH};
 class PWire : public LineInfo {
 
     public:
-      PWire(const pform_name_t&hname,
+      PWire(perm_string name,
 	    NetNet::Type t,
 	    NetNet::PortType pt,
 	    ivl_variable_type_t dt);
 
 	// Return a hierarchical name.
-      const pform_name_t&path() const;
+      perm_string basename() const;
 
       NetNet::Type get_wire_type() const;
       bool set_wire_type(NetNet::Type);
@@ -90,7 +90,7 @@ class PWire : public LineInfo {
       NetNet* elaborate_sig(Design*, NetScope*scope) const;
 
     private:
-      pform_name_t hname_;
+      perm_string name_;
       NetNet::Type type_;
       NetNet::PortType port_type_;
       ivl_variable_type_t data_type_;

diff --git a/Statement.h b/Statement.h
@@ -84,6 +84,7 @@ class Statement : public LineInfo {
       virtual void dump(ostream&out, unsigned ind) const;
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
+      virtual void elaborate_sig(Design*des, NetScope*scope) const;
 };
 
 /*
@@ -166,6 +167,7 @@ class PBlock  : public PScope, public Statement {
       virtual void dump(ostream&out, unsigned ind) const;
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
+      virtual void elaborate_sig(Design*des, NetScope*scope) const;
 
     private:
       const BL_TYPE bl_type_;
@@ -217,6 +219,7 @@ class PCase  : public Statement {
 
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
+      virtual void elaborate_sig(Design*des, NetScope*scope) const;
       virtual void dump(ostream&out, unsigned ind) const;
 
     private:
@@ -252,6 +255,7 @@ class PCondit  : public Statement {
 
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
+      virtual void elaborate_sig(Design*des, NetScope*scope) const;
       virtual void dump(ostream&out, unsigned ind) const;
 
     private:
@@ -286,6 +290,7 @@ class PDelayStatement  : public Statement {
       virtual void dump(ostream&out, unsigned ind) const;
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
+      virtual void elaborate_sig(Design*des, NetScope*scope) const;
 
     private:
       PExpr*delay_;
@@ -333,6 +338,7 @@ class PEventStatement  : public Statement {
       virtual void dump(ostream&out, unsigned ind) const;
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
+      virtual void elaborate_sig(Design*des, NetScope*scope) const;
 
 	// This method is used to elaborate, but attach a previously
 	// elaborated statement to the event.
@@ -366,6 +372,7 @@ class PForever : public Statement {
 
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
+      virtual void elaborate_sig(Design*des, NetScope*scope) const;
       virtual void dump(ostream&out, unsigned ind) const;
 
     private:
@@ -381,6 +388,7 @@ class PForStatement  : public Statement {
 
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
+      virtual void elaborate_sig(Design*des, NetScope*scope) const;
       virtual void dump(ostream&out, unsigned ind) const;
 
     private:

diff --git a/design_dump.cc b/design_dump.cc
@@ -309,8 +309,14 @@ void NetPow::dump_node(ostream&o, unsigned ind) const
 {
       o << setw(ind) << "" << "LPM_POW (NetPow): " << name()
 	<< " scope=" << scope_path(scope())
-	<< " delay=(" << *rise_time() << "," << *fall_time() << ","
-	<<  *decay_time() << ")"  << endl;
+	<< " delay=(";
+      if (rise_time())
+	    o << *rise_time() << "," << *fall_time() << ","
+	      <<  *decay_time();
+      else
+	    o << "0,0,0";
+
+      o << ")"  << endl;
       dump_node_pins(o, ind+4);
       dump_obj_attr(o, ind+4);
 }
@@ -980,7 +986,10 @@ void NetScope::dump(ostream&o) const
 		  o << "    MISSING FUNCTION DEFINITION" << endl;
 	    break;
 	  case TASK:
-	    task_def()->dump(o, 4);
+	    if (task_def())
+		  task_def()->dump(o, 4);
+	    else
+		  o << "    MISSING TASK DEFINITION" << endl;
 	    break;
 	  default:
 	    break;