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Factor out common code for warning about inconsistent timescales.
Also reword the warning for SystemVerilog, where `timescale is not the only (or indeed preferred) way of specifying timescales.
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Original file line number | Diff line number | Diff line change |
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@@ -1,5 +1,5 @@ | ||
/* | ||
* Copyright (c) 1999-2011 Stephen Williams ([email protected]) | ||
* Copyright (c) 1999-2017 Stephen Williams ([email protected]) | ||
* | ||
* This source code is free software; you can redistribute it | ||
* and/or modify it in source code form under the terms of the GNU | ||
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@@ -26,11 +26,6 @@ | |
# include "verinum.h" | ||
# include "netmisc.h" | ||
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bool dly_used_no_timescale = false; | ||
bool dly_used_timescale = false; | ||
bool display_ts_dly_warning = true; | ||
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PDelays::PDelays() | ||
{ | ||
delete_flag_ = true; | ||
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@@ -80,19 +75,7 @@ static NetExpr*calculate_val(Design*des, NetScope*scope, PExpr*expr) | |
{ | ||
NetExpr*dex = elab_and_eval(des, scope, expr, -1); | ||
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/* Print a warning if we find default and `timescale based | ||
* delays in the design, since this is likely an error. */ | ||
if (scope->time_from_timescale()) dly_used_timescale = true; | ||
else dly_used_no_timescale = true; | ||
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if (display_ts_dly_warning && | ||
dly_used_no_timescale && dly_used_timescale) { | ||
cerr << "warning: Found both default and " | ||
"`timescale based delays. Use" << endl; | ||
cerr << " -Wtimescale to find the " | ||
"module(s) with no `timescale." << endl; | ||
display_ts_dly_warning = false; | ||
} | ||
check_for_inconsistent_delays(scope); | ||
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/* If the delay expression is a real constant or vector | ||
constant, then evaluate it, scale it to the local time | ||
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,5 +1,5 @@ | ||
/* | ||
* Copyright (c) 2001-2016 Stephen Williams ([email protected]) | ||
* Copyright (c) 2001-2017 Stephen Williams ([email protected]) | ||
* | ||
* This source code is free software; you can redistribute it | ||
* and/or modify it in source code form under the terms of the GNU | ||
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@@ -1665,3 +1665,38 @@ NetScope* find_method_containing_scope(const LineInfo&, NetScope*scope) | |
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return scope; | ||
} | ||
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/* | ||
* Print a warning if we find a mixture of default and explicit timescale | ||
* based delays in the design, since this is likely an error. | ||
*/ | ||
void check_for_inconsistent_delays(NetScope*scope) | ||
{ | ||
static bool used_implicit_timescale = false; | ||
static bool used_explicit_timescale = false; | ||
static bool display_ts_dly_warning = true; | ||
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if (scope->time_from_timescale()) | ||
used_explicit_timescale = true; | ||
else | ||
used_implicit_timescale = true; | ||
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if (display_ts_dly_warning && | ||
used_explicit_timescale && | ||
used_implicit_timescale) { | ||
if (gn_system_verilog()) { | ||
cerr << "warning: Found both default and explicit " | ||
"timescale based delays. Use" << endl; | ||
cerr << " : -Wtimescale to find the design " | ||
"element(s) with no explicit" << endl; | ||
cerr << " : timescale." << endl; | ||
} else { | ||
cerr << "warning: Found both default and " | ||
"`timescale based delays. Use" << endl; | ||
cerr << " : -Wtimescale to find the " | ||
"module(s) with no `timescale." << endl; | ||
} | ||
display_ts_dly_warning = false; | ||
} | ||
} |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,7 +1,7 @@ | ||
#ifndef IVL_netmisc_H | ||
#define IVL_netmisc_H | ||
/* | ||
* Copyright (c) 1999-2016 Stephen Williams ([email protected]) | ||
* Copyright (c) 1999-2017 Stephen Williams ([email protected]) | ||
* | ||
* This source code is free software; you can redistribute it | ||
* and/or modify it in source code form under the terms of the GNU | ||
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@@ -378,10 +378,6 @@ const char *human_readable_op(const char op, bool unary = false); | |
enum const_bool { C_NON, C_0, C_1, C_X }; | ||
const_bool const_logical(const NetExpr*expr); | ||
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extern bool dly_used_no_timescale; | ||
extern bool dly_used_timescale; | ||
extern bool display_ts_dly_warning; | ||
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/* | ||
* When scaling a real value to a time we need to do some standard | ||
* processing. | ||
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@@ -409,4 +405,10 @@ extern void assign_unpacked_with_bufz(Design*des, NetScope*scope, | |
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extern NetPartSelect* detect_partselect_lval(Link&pin); | ||
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/* | ||
* Print a warning if we find a mixture of default and explicit timescale | ||
* based delays in the design, since this is likely an error. | ||
*/ | ||
extern void check_for_inconsistent_delays(NetScope*scope); | ||
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#endif /* IVL_netmisc_H */ |