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Remove svector class from Module.h
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The goal is to completely remove the svector class because the standard
vector class works perfectly well. This removes the uses in the Module.h
header file.
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@steveicarus
steveicarus committed Nov 3, 2008
1 parent 77eb68d commit ddb2c60
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Showing 9 changed files with 73 additions and 75 deletions.
12 changes: 6 additions & 6 deletions Module.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -43,18 +43,18 @@ void Module::add_gate(PGate*gate)

unsigned Module::port_count() const
{
return ports.count();
return ports.size();
}

/*
* Return the array of PEIdent object that are at this port of the
* module. If the port is internally unconnected, return an empty
* array.
*/
const svector<PEIdent*>& Module::get_port(unsigned idx) const
const vector<PEIdent*>& Module::get_port(unsigned idx) const
{
assert(idx < ports.count());
static svector<PEIdent*> zero;
assert(idx < ports.size());
static const vector<PEIdent*> zero;

if (ports[idx])
return ports[idx]->expr;
Expand All @@ -65,7 +65,7 @@ const svector<PEIdent*>& Module::get_port(unsigned idx) const
unsigned Module::find_port(const char*name) const
{
assert(name != 0);
for (unsigned idx = 0 ; idx < ports.count() ; idx += 1) {
for (unsigned idx = 0 ; idx < ports.size() ; idx += 1) {
if (ports[idx] == 0) {
/* It is possible to have undeclared ports. These
are ports that are skipped in the declaration,
Expand All @@ -79,7 +79,7 @@ unsigned Module::find_port(const char*name) const
return idx;
}

return ports.count();
return ports.size();
}


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8 changes: 4 additions & 4 deletions Module.h
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Original file line number Diff line number Diff line change
Expand Up @@ -22,8 +22,8 @@

# include <list>
# include <map>
# include <vector>
# include <utility>
# include "svector.h"
# include "StringHeap.h"
# include "HName.h"
# include "named.h"
Expand Down Expand Up @@ -59,7 +59,7 @@ class Module : public PScope, public LineInfo {
public:
struct port_t {
perm_string name;
svector<PEIdent*> expr;
vector<PEIdent*> expr;
};

public:
Expand Down Expand Up @@ -98,7 +98,7 @@ class Module : public PScope, public LineInfo {

/* This is an array of port descriptors, which is in turn a
named array of PEident pointers. */
svector<port_t*> ports;
vector<port_t*> ports;

map<perm_string,PExpr*> attributes;

Expand Down Expand Up @@ -126,7 +126,7 @@ class Module : public PScope, public LineInfo {
void add_gate(PGate*gate);

unsigned port_count() const;
const svector<PEIdent*>& get_port(unsigned idx) const;
const vector<PEIdent*>& get_port(unsigned idx) const;
unsigned find_port(const char*name) const;

PGate* get_gate(perm_string name);
Expand Down
6 changes: 3 additions & 3 deletions elab_sig.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -150,7 +150,7 @@ bool Module::elaborate_sig(Design*des, NetScope*scope) const

// Scan all the ports of the module, and make sure that each
// is connected to wires that have port declarations.
for (unsigned idx = 0 ; idx < ports.count() ; idx += 1) {
for (unsigned idx = 0 ; idx < ports.size() ; idx += 1) {
Module::port_t*pp = ports[idx];
if (pp == 0)
continue;
Expand All @@ -159,7 +159,7 @@ bool Module::elaborate_sig(Design*des, NetScope*scope) const
// expression are all identifiers that should reference
// wires within the scope.
map<perm_string,PWire*>::const_iterator wt;
for (unsigned cc = 0 ; cc < pp->expr.count() ; cc += 1) {
for (unsigned cc = 0 ; cc < pp->expr.size() ; cc += 1) {
pform_name_t port_path (pp->expr[cc]->path());
// A concatenated wire of a port really should not
// have any hierarchy.
Expand Down Expand Up @@ -365,7 +365,7 @@ bool PGModule::elaborate_sig_mod_(Design*des, NetScope*scope,

NetScope::scope_vec_t instance = scope->instance_arrays[get_name()];

for (unsigned idx = 0 ; idx < instance.count() ; idx += 1) {
for (unsigned idx = 0 ; idx < instance.size() ; idx += 1) {
// I know a priori that the elaborate_scope created the scope
// already, so just look it up as a child of the current scope.
NetScope*my_scope = instance[idx];
Expand Down
65 changes: 32 additions & 33 deletions elaborate.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -938,7 +938,7 @@ NetNet*PGModule::resize_net_to_port_(Design*des, NetScope*scope,
return tmp;
}

static bool need_bufz_for_input_port(const svector<NetNet*>&prts)
static bool need_bufz_for_input_port(const vector<NetNet*>&prts)
{
if (prts[0]->port_type() != NetNet::PINPUT)
return false;
Expand Down Expand Up @@ -1051,7 +1051,7 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
// later.

NetScope::scope_vec_t&instance = scope->instance_arrays[get_name()];
for (unsigned inst = 0 ; inst < instance.count() ; inst += 1) {
for (unsigned inst = 0 ; inst < instance.size() ; inst += 1) {
rmod->elaborate(des, instance[inst]);
}

Expand Down Expand Up @@ -1079,8 +1079,8 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
// input. If so, consider printing a port binding
// warning.
if (warn_portbinding) {
svector<PEIdent*> mport = rmod->get_port(idx);
if (mport.count() == 0)
vector<PEIdent*> mport = rmod->get_port(idx);
if (mport.size() == 0)
continue;

perm_string pname = peek_tail_name(mport[0]->path());
Expand All @@ -1105,26 +1105,26 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
// Inside the module, the port is zero or more signals
// that were already elaborated. List all those signals
// and the NetNet equivalents, for all the instances.
svector<PEIdent*> mport = rmod->get_port(idx);
svector<NetNet*>prts (mport.count() * instance.count());
vector<PEIdent*> mport = rmod->get_port(idx);
vector<NetNet*> prts (mport.size() * instance.size());

if (debug_elaborate) {
cerr << get_fileline() << ": debug: " << get_name()
<< ": Port " << idx << " has " << prts.count()
<< ": Port " << idx << " has " << prts.size()
<< " sub-ports." << endl;
}

// Count the internal vector bits of the port.
unsigned prts_vector_width = 0;

for (unsigned inst = 0 ; inst < instance.count() ; inst += 1) {
for (unsigned inst = 0 ; inst < instance.size() ; inst += 1) {
// Scan the instances from MSB to LSB. The port
// will be assembled in that order as well.
NetScope*inst_scope = instance[instance.count()-inst-1];
NetScope*inst_scope = instance[instance.size()-inst-1];

// Scan the module sub-ports for this instance...
for (unsigned ldx = 0 ; ldx < mport.count() ; ldx += 1) {
unsigned lbase = inst * mport.count();
for (unsigned ldx = 0 ; ldx < mport.size() ; ldx += 1) {
unsigned lbase = inst * mport.size();
PEIdent*pport = mport[ldx];
assert(pport);
prts[lbase + ldx]
Expand All @@ -1147,18 +1147,18 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
// We know by design that each instance has the same
// width port. Therefore, the prts_pin_count must be an
// even multiple of the instance count.
assert(prts_vector_width % instance.count() == 0);
assert(prts_vector_width % instance.size() == 0);

unsigned desired_vector_width = prts_vector_width;
if (instance.count() != 1)
if (instance.size() != 1)
desired_vector_width = 0;

// Elaborate the expression that connects to the
// module[s] port. sig is the thing outside the module
// that connects to the port.

NetNet*sig;
if ((prts.count() == 0)
if ((prts.size() == 0)
|| (prts[0]->port_type() == NetNet::PINPUT)) {

/* Input to module. elaborate the expression to
Expand Down Expand Up @@ -1263,21 +1263,21 @@ v NOTE that this also handles the case that the
assert(sig);

#ifndef NDEBUG
if ((prts.count() >= 1)
if ((prts.size() >= 1)
&& (prts[0]->port_type() != NetNet::PINPUT)) {
assert(sig->type() != NetNet::REG);
}
#endif

/* If we are working with an instance array, then the
signal width must match the port width exactly. */
if ((instance.count() != 1)
if ((instance.size() != 1)
&& (sig->vector_width() != prts_vector_width)
&& (sig->vector_width() != prts_vector_width/instance.count())) {
&& (sig->vector_width() != prts_vector_width/instance.size())) {
cerr << pins[idx]->get_fileline() << ": error: "
<< "Port expression width " << sig->vector_width()
<< " does not match expected width "<< prts_vector_width
<< " or " << (prts_vector_width/instance.count())
<< " or " << (prts_vector_width/instance.size())
<< "." << endl;
des->errors += 1;
continue;
Expand All @@ -1292,7 +1292,7 @@ v NOTE that this also handles the case that the
// Check that the parts have matching pin counts. If
// not, they are different widths. Note that idx is 0
// based, but users count parameter positions from 1.
if ((instance.count() == 1)
if ((instance.size() == 1)
&& (prts_vector_width != sig->vector_width())) {
const char *tmp3 = rmod->ports[idx]->name.str();
bool as_signed = false;
Expand Down Expand Up @@ -1363,15 +1363,15 @@ v NOTE that this also handles the case that the
// Connect this many of the port pins. If the expression
// is too small, then reduce the number of connects.
unsigned ccount = prts_vector_width;
if (instance.count() == 1 && sig->vector_width() < ccount)
if (instance.size() == 1 && sig->vector_width() < ccount)
ccount = sig->vector_width();

// The spin_modulus is the width of the signal (not the
// port) if this is an instance array. This causes
// signals wide enough for a single instance to be
// connected to all the instances.
unsigned spin_modulus = prts_vector_width;
if (instance.count() != 1)
if (instance.size() != 1)
spin_modulus = sig->vector_width();

// Now scan the concatenation that makes up the port,
Expand All @@ -1383,41 +1383,40 @@ v NOTE that this also handles the case that the
NetConcat*ctmp;
unsigned spin = 0;

if (prts.count() == 1) {
if (prts.size() == 1) {

// The simplest case, there are no
// parts/concatenations on the inside of the
// module, so the port and sig need simply be
// connected directly.
connect(prts[0]->pin(0), sig->pin(0));

} else if (sig->vector_width()==prts_vector_width/instance.count()
&& prts.count()/instance.count() == 1) {
} else if (sig->vector_width()==prts_vector_width/instance.size()
&& prts.size()/instance.size() == 1) {

if (debug_elaborate){
cerr << get_fileline() << ": debug: " << get_name()
<< ": Replicating " << prts_vector_width
<< " bits across all "
<< prts_vector_width/instance.count()
<< prts_vector_width/instance.size()
<< " sub-ports." << endl;
}

// The signal width is exactly the width of a
// single instance of the port. In this case,
// connect the sig to all the ports identically.
for (unsigned ldx = 0 ; ldx < prts.count() ; ldx += 1)
for (unsigned ldx = 0 ; ldx < prts.size() ; ldx += 1)
connect(prts[ldx]->pin(0), sig->pin(0));

} else switch (prts[0]->port_type()) {
case NetNet::POUTPUT:
ctmp = new NetConcat(scope, scope->local_symbol(),
prts_vector_width,
prts.count());
prts_vector_width, prts.size());
des->add_node(ctmp);
connect(ctmp->pin(0), sig->pin(0));
for (unsigned ldx = 0 ; ldx < prts.count() ; ldx += 1) {
for (unsigned ldx = 0 ; ldx < prts.size() ; ldx += 1) {
connect(ctmp->pin(ldx+1),
prts[prts.count()-ldx-1]->pin(0));
prts[prts.size()-ldx-1]->pin(0));
}
break;

Expand All @@ -1426,13 +1425,13 @@ v NOTE that this also handles the case that the
cerr << get_fileline() << ": debug: " << get_name()
<< ": Dividing " << prts_vector_width
<< " bits across all "
<< prts_vector_width/instance.count()
<< prts_vector_width/instance.size()
<< " input sub-ports of port "
<< idx << "." << endl;
}

for (unsigned ldx = 0 ; ldx < prts.count() ; ldx += 1) {
NetNet*sp = prts[prts.count()-ldx-1];
for (unsigned ldx = 0 ; ldx < prts.size() ; ldx += 1) {
NetNet*sp = prts[prts.size()-ldx-1];
NetPartSelect*ptmp = new NetPartSelect(sig, spin,
sp->vector_width(),
NetPartSelect::VP);
Expand Down
2 changes: 1 addition & 1 deletion netlist.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -829,7 +829,7 @@ class NetScope : public Attrib {

/* Module instance arrays are collected here for access during
the multiple elaboration passes. */
typedef svector<NetScope*> scope_vec_t;
typedef vector<NetScope*> scope_vec_t;
map<perm_string, scope_vec_t>instance_arrays;

/* Loop generate uses this as scratch space during
Expand Down
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