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Add support for HSE bypass on STM32. #709

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Add support for HSE bypass on STM32. #709

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2 changes: 2 additions & 0 deletions README.md
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Original file line number Diff line number Diff line change
Expand Up @@ -144,6 +144,8 @@ See the [Kalico Additions document](https://docs.kalico.gg/Kalico_Additions.html

- [extruder: cold_extrude](https://github.com/KalicoCrew/kalico/pull/750)

- [core: support for STM32 MCUs with oscillators rather than crystals](https://github.com/KalicoCrew/kalico/pull/709)

If you're feeling adventurous, take a peek at the extra features in the bleeding-edge-v2 branch [feature documentation](docs/Bleeding_Edge.md)
and [feature configuration reference](docs/Config_Reference_Bleeding_Edge.md):

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20 changes: 14 additions & 6 deletions src/stm32/Kconfig
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Expand Up @@ -352,17 +352,17 @@ config ARMCM_RAM_VECTORTABLE
choice
prompt "Clock Reference" if LOW_LEVEL_OPTIONS
config STM32_CLOCK_REF_8M
bool "8 MHz crystal"
bool "8 MHz external"
config STM32_CLOCK_REF_12M
bool "12 MHz crystal"
bool "12 MHz external"
config STM32_CLOCK_REF_16M
bool "16 MHz crystal"
bool "16 MHz external"
config STM32_CLOCK_REF_20M
bool "20 MHz crystal"
bool "20 MHz external"
config STM32_CLOCK_REF_24M
bool "24 MHz crystal"
bool "24 MHz external"
config STM32_CLOCK_REF_25M
bool "25 MHz crystal"
bool "25 MHz external"
config STM32_CLOCK_REF_INTERNAL
bool "Internal clock"
endchoice
Expand All @@ -385,6 +385,14 @@ config STM32F0_TRIM
Default is 16 (use factory default). Each increment increases
the clock rate by ~240KHz.

choice
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liampwll marked this conversation as resolved.
prompt "External Clock Type" if LOW_LEVEL_OPTIONS && !STM32_CLOCK_REF_INTERNAL && MACH_STM32G474
default STM32_CLOCK_HSE_CRYSTAL
config STM32_CLOCK_HSE_CRYSTAL
bool "HSE Crystal"
config STM32_CLOCK_HSE_BYPASS
bool "HSE Bypass"
endchoice

######################################################################
# Communication inteface
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11 changes: 9 additions & 2 deletions src/stm32/stm32g4.c
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Expand Up @@ -76,8 +76,12 @@ gpio_clock_enable(GPIO_TypeDef *regs)
RCC->AHB2ENR;
}

#if !CONFIG_STM32_CLOCK_REF_INTERNAL
DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PF0,PF1");
#if CONFIG_STM32_CLOCK_REF_INTERNAL
// No pins required.
#elif CONFIG_STM32_CLOCK_HSE_BYPASS
DECL_CONSTANT_STR("RESERVE_PINS_hse_clock", "PF0");
#else // CONFIG_STM32_CLOCK_HSE_CRYSTAL
DECL_CONSTANT_STR("RESERVE_PINS_hse_clock", "PF0,PF1");
#endif

static void
Expand All @@ -94,6 +98,9 @@ enable_clock_stm32g4(void)
pll_base = 4000000;
#endif
uint32_t div = CONFIG_CLOCK_REF_FREQ / pll_base - 1;
if (CONFIG_STM32_CLOCK_HSE_BYPASS) {
RCC->CR |= RCC_CR_HSEBYP;
}
RCC->CR |= RCC_CR_HSEON;
while (!(RCC->CR & RCC_CR_HSERDY))
;
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