Add VideoStrong KM5 (videostrong-km5) #27
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Device specifications: https://whatismyphone.net/vendors/videostrong/km5-android-tv-box-km5 The manufacturer's website is here: https://www.videostrong.com/ (Unfortunately the original device page has been taken down) This is a board that I've ripped the NAND module (usually has one) off of it so I can't rely on the original bootloader tricks to get a newer version on U-Boot running on it. Thankfully I was able to get it going by dumping and extracting the necessary bootloader parts from the original firmware dump I found somewhere and I've tested that it works. The acs.bin dump is based on the ddrs_ tables found in bl2.bin, through crude hexediting I was able to transfer that over to the Le Potato's acs.bin, I've tested that and it seems to work. The rest of the files are original from the ROM dump.
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@nikp123 As this wasn't sourced the normal way (blobs extracted from vendor build tools) can you please provide a more detailed description of how |
No problem:
3.4 Open our target |
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It's a bit of an process but hopefully comprehensible, but I didn't feel writing a whole article to explain the reasoning behind every step. |
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@nikp123 The acs is not just that Hope this helps: I wrote an ACS parsing tool a long while ago. See https://git.vitali64.duckdns.org/utils/acsbaby.git it currently supports gxbb (S905) and gxl (S905X/S805X/S805Y/...) |
Sorry for the late reply, was busy with some stuff IRL. But I've used your tool on the original decrypted dump, so these values should? be correct. // Binary type: bl2
/* acs.c
* ACSBaby: Parse Amlogic ACS.bin - https://git.vitali64.duckdns.org/utils/acsbaby.git
* File: /home/nikp123/Downloads/bl2.bin - Type: bl2
*/
#include <asm/arch/acs.h>
#include <asm/arch/timing.h>
#include "timing.c"
struct acs_setting __acs_set = {
.acs_magic = "acs__",
.chip_type = 0x24,
.version = 1,
.acs_set_length = 0x100,
.ddr_magic = "ddrs_",
.ddr_set_version = 2,
.ddr_set_length = 0x180,
.ddr_set_addr = (unsigned long)(&__ddr_setting), /* 0xd9009000 */
.ddrt_magic = "ddrt_",
.ddrt_set_version = 1,
.ddrt_set_length = 0x150,
.ddrt_set_addr = (unsigned long)(&__ddr_timming), /* 0xd9009180 */
.pll_magic = "pll__",
.pll_set_version = 1,
.pll_set_length = 0x40,
.pll_set_addr = (unsigned long)(&__pll_setting), /* 0xd90092d0 */
};
/* timing.c
* ACSBaby: Parse Amlogic ACS.bin - https://git.vitali64.duckdns.org/utils/acsbaby.git
* File: /home/nikp123/Downloads/bl2.bin - Type: bl2
*/
#include <asm/arch/timing.h>
#include <asm/arch/ddr_define.h>
/* "ddrs_" structure */
ddr_set_t __ddr_setting = {
.ddr_channel_set = 0xf
.ddr_type = 0x0
.ddr_2t_mode = 0x1
.ddr_full_test = 0x0
.ddr_size_detect = 0x1
.ddr_drv = 0x0
.ddr_odt = 0x2
.ddr_timing_ind = 0x0
.ddr_size = 0x0
.ddr_clk = 0x2d0
.ddr_base_addr = 0x0
.ddr_start_offset = 0x1000000
.ddr_pll_ctrl = 0x0
.ddr_dmc_ctrl = 0x0
.ddr0_addrmap[0] = 0x0
.ddr0_addrmap[1] = 0x0
.ddr0_addrmap[2] = 0x0
.ddr0_addrmap[3] = 0x0
.ddr0_addrmap[4] = 0x0
.ddr1_addrmap[0] = 0x0
.ddr1_addrmap[1] = 0x0
.ddr1_addrmap[2] = 0x0
.ddr1_addrmap[3] = 0x0
.ddr1_addrmap[4] = 0x0
.t_pub_ptr[0] = 0xa005006
.t_pub_ptr[1] = 0x3e80078
.t_pub_ptr[2] = 0x0
.t_pub_ptr[3] = 0x8804e20
.t_pub_ptr[4] = 0xb403e8
.t_pub_mr[0] = 0x1e04
.t_pub_mr[1] = 0x46
.t_pub_mr[2] = 0x20
.t_pub_mr[3] = 0x0
.t_pub_mr[4] = 0x0
.t_pub_mr[5] = 0x0
.t_pub_mr[6] = 0x0
.t_pub_mr[7] = 0x0
.t_pub_odtcr = 0x30000
.t_pub_dtpr[0] = 0x0
.t_pub_dtpr[1] = 0x0
.t_pub_dtpr[2] = 0x0
.t_pub_dtpr[3] = 0x0
.t_pub_dtpr[4] = 0x0
.t_pub_dtpr[5] = 0x0
.t_pub_dtpr[6] = 0x0
.t_pub_dtpr[7] = 0x0
.t_pub_pgcr0 = 0x7d81e3f
.t_pub_pgcr1 = 0x2004620
.t_pub_pgcr2 = 0xf05f97
.t_pub_pgcr3 = 0xc0aae860
.t_pub_dxccr = 0x20c01ee4
.t_pub_dtcr0 = 0x80003187
.t_pub_dtcr1 = 0x10237
.t_pub_aciocr[0] = 0x0
.t_pub_aciocr[1] = 0x0
.t_pub_aciocr[2] = 0x0
.t_pub_aciocr[3] = 0x0
.t_pub_aciocr[4] = 0x0
.t_pub_dx0gcr[0] = 0x0
.t_pub_dx0gcr[1] = 0x0
.t_pub_dx0gcr[2] = 0x0
.t_pub_dx1gcr[0] = 0x0
.t_pub_dx1gcr[1] = 0x0
.t_pub_dx1gcr[2] = 0x0
.t_pub_dx2gcr[0] = 0x0
.t_pub_dx2gcr[1] = 0x0
.t_pub_dx2gcr[2] = 0x0
.t_pub_dx3gcr[0] = 0x0
.t_pub_dx3gcr[1] = 0x0
.t_pub_dx3gcr[2] = 0x0
.t_pub_dcr = 0xb
.t_pub_dtar = 0x0
.t_pub_dsgcr = 0x20641b
.t_pub_zq0pr = 0x18
.t_pub_zq1pr = 0x3d
.t_pub_zq2pr = 0x3d
.t_pub_zq3pr = 0x1d
.t_pub_vtcr1 = 0xfc00172
.t_pctl0_1us_pck = 0x168
.t_pctl0_100ns_pck = 0x24
.t_pctl0_init_us = 0x2
.t_pctl0_rsth_us = 0x2
.t_pctl0_mcfg = 0xa2f01
.t_pctl0_mcfg1 = 0x0
.t_pctl0_scfg = 0xf01
.t_pctl0_sctl = 0x1
.t_pctl0_ppcfg = 0x0
.t_pctl0_dfistcfg0 = 0x4
.t_pctl0_dfistcfg1 = 0x1
.t_pctl0_dfitctrldelay = 0x2
.t_pctl0_dfitphywrdata = 0x2
.t_pctl0_dfitphywrlta = 0x7
.t_pctl0_dfitrddataen = 0x8
.t_pctl0_dfitphyrdlat = 0x16
.t_pctl0_dfitdramclkdis = 0x1
.t_pctl0_dfitdramclken = 0x1
.t_pctl0_dfitphyupdtype0= 0x10
.t_pctl0_dfitphyupdtype1= 0x10
.t_pctl0_dfitctrlupdmin = 0x10
.t_pctl0_dfitctrlupdmax = 0x40
.t_pctl0_dfiupdcfg = 0x3
.t_pctl0_cmdtstaten = 0x1
.t_ddr_align = 0x0
.t_pctl0_dfiodtcfg = 0x808
.t_pctl0_dfiodtcfg1 = 0x60000
.t_pctl0_dfilpcfg0 = 0x3107d131
.t_pub_acbdlr0 = 0x3f
.t_pub_aclcdlr = 0x1b
.ddr_func = 0x80000000
.wr_adj_per[0] = 0x64
.wr_adj_per[1] = 0x64
.wr_adj_per[2] = 0x5f
.wr_adj_per[3] = 0x5f
.wr_adj_per[4] = 0x5f
.wr_adj_per[5] = 0x5f
.rd_adj_per[0] = 0x64
.rd_adj_per[1] = 0x64
.rd_adj_per[2] = 0x5f
.rd_adj_per[3] = 0x5f
.rd_adj_per[4] = 0x5f
.rd_adj_per[5] = 0x5f
.ddr4_clk = 0x3f0
.ddr4_drv = 0x0
.ddr4_odt = 0x1
.t_pub_acbdlr3 = 0x0
.t_pub_soc_vref_dram_vref = 0x0
.t_pub_soc_vref_dram_vref_rank1 = 0x0
.wr_adj_per_rank1[0] = 0x0
.wr_adj_per_rank1[1] = 0x0
.wr_adj_per_rank1[2] = 0x0
.wr_adj_per_rank1[3] = 0x0
.wr_adj_per_rank1[4] = 0x0
.wr_adj_per_rank1[5] = 0x0
.rd_adj_per_rank1[0] = 0x0
.rd_adj_per_rank1[1] = 0x0
.rd_adj_per_rank1[2] = 0x0
.rd_adj_per_rank1[3] = 0x0
.rd_adj_per_rank1[4] = 0x0
.rd_adj_per_rank1[5] = 0x0
};
/* "ddrt_" structure */
ddr_timing_t __ddr_timming[] = {
/* "ddrt_" array index: 0 */
{
.identifier = 0x7,
.cfg_ddr_rtp = 0x6,
.cfg_ddr_wtr = 0x7,
.cfg_ddr_rp = 0x7,
.cfg_ddr_rcd = 0x7,
.cfg_ddr_ras = 0x14,
.cfg_ddr_rrd = 0x6,
.cfg_ddr_rc = 0x1b,
.cfg_ddr_mrd = 0x4,
.cfg_ddr_mod = 0xc,
.cfg_ddr_faw = 0x1b,
.cfg_ddr_wlmrd = 0x28,
.cfg_ddr_wlo = 0x6,
.cfg_ddr_xp = 0x7,
.cfg_ddr_rfc = 0xa0,
.cfg_ddr_xs = 0x200,
.cfg_ddr_dllk = 0x200,
.cfg_ddr_cke = 0x4,
.cfg_ddr_rtodt = 0x0,
.cfg_ddr_rtw = 0x4,
.cfg_ddr_refi = 0x4e,
.cfg_ddr_refi_mddr3 = 0x4,
.cfg_ddr_cl = 0x7,
.cfg_ddr_wr = 0xc,
.cfg_ddr_cwl = 0x5,
.cfg_ddr_al = 0x0,
.cfg_ddr_dqs = 0x4,
.cfg_ddr_cksre = 0xf,
.cfg_ddr_cksrx = 0xf,
.cfg_ddr_zqcs = 0x40,
.cfg_ddr_xpdll = 0x14,
.cfg_ddr_exsr = 0x200,
.cfg_ddr_zqcl = 0x200,
.cfg_ddr_zqcsi = 0x3e8,
.cfg_ddr_tccdl = 0x0,
.cfg_ddr_tdqsck = 0x0,
.cfg_ddr_tdqsckmax = 0x0,
.rsv_char = 0x0,
.rsv_int = 0x0,
},
/* "ddrt_" array index: 1 */
{
.identifier = 0x9,
.cfg_ddr_rtp = 0x6,
.cfg_ddr_wtr = 0x7,
.cfg_ddr_rp = 0x9,
.cfg_ddr_rcd = 0x9,
.cfg_ddr_ras = 0x1b,
.cfg_ddr_rrd = 0x6,
.cfg_ddr_rc = 0x21,
.cfg_ddr_mrd = 0x4,
.cfg_ddr_mod = 0xc,
.cfg_ddr_faw = 0x1e,
.cfg_ddr_wlmrd = 0x28,
.cfg_ddr_wlo = 0x6,
.cfg_ddr_xp = 0x7,
.cfg_ddr_rfc = 0xc4,
.cfg_ddr_xs = 0x200,
.cfg_ddr_dllk = 0x200,
.cfg_ddr_cke = 0x4,
.cfg_ddr_rtodt = 0x0,
.cfg_ddr_rtw = 0x6,
.cfg_ddr_refi = 0x4e,
.cfg_ddr_refi_mddr3 = 0x4,
.cfg_ddr_cl = 0x9,
.cfg_ddr_wr = 0xc,
.cfg_ddr_cwl = 0x7,
.cfg_ddr_al = 0x0,
.cfg_ddr_dqs = 0x17,
.cfg_ddr_cksre = 0xf,
.cfg_ddr_cksrx = 0xf,
.cfg_ddr_zqcs = 0x40,
.cfg_ddr_xpdll = 0x14,
.cfg_ddr_exsr = 0x200,
.cfg_ddr_zqcl = 0x88,
.cfg_ddr_zqcsi = 0x3e8,
.cfg_ddr_tccdl = 0x0,
.cfg_ddr_tdqsck = 0x0,
.cfg_ddr_tdqsckmax = 0x0,
.rsv_char = 0x0,
.rsv_int = 0x0,
},
/* "ddrt_" array index: 2 */
{
.identifier = 0xb,
.cfg_ddr_rtp = 0x7,
.cfg_ddr_wtr = 0x7,
.cfg_ddr_rp = 0xb,
.cfg_ddr_rcd = 0xb,
.cfg_ddr_ras = 0x23,
.cfg_ddr_rrd = 0x7,
.cfg_ddr_rc = 0x2d,
.cfg_ddr_mrd = 0x6,
.cfg_ddr_mod = 0xc,
.cfg_ddr_faw = 0x21,
.cfg_ddr_wlmrd = 0x28,
.cfg_ddr_wlo = 0x7,
.cfg_ddr_xp = 0x5,
.cfg_ddr_rfc = 0x118,
.cfg_ddr_xs = 0x200,
.cfg_ddr_dllk = 0x200,
.cfg_ddr_cke = 0x4,
.cfg_ddr_rtodt = 0x0,
.cfg_ddr_rtw = 0x7,
.cfg_ddr_refi = 0x4e,
.cfg_ddr_refi_mddr3 = 0x4,
.cfg_ddr_cl = 0xb,
.cfg_ddr_wr = 0xc,
.cfg_ddr_cwl = 0x8,
.cfg_ddr_al = 0x0,
.cfg_ddr_dqs = 0x17,
.cfg_ddr_cksre = 0xf,
.cfg_ddr_cksrx = 0xf,
.cfg_ddr_zqcs = 0x40,
.cfg_ddr_xpdll = 0x17,
.cfg_ddr_exsr = 0x200,
.cfg_ddr_zqcl = 0x88,
.cfg_ddr_zqcsi = 0x3e8,
.cfg_ddr_tccdl = 0x0,
.cfg_ddr_tdqsck = 0x0,
.cfg_ddr_tdqsckmax = 0x0,
.rsv_char = 0x0,
.rsv_int = 0x0,
},
/* "ddrt_" array index: 3 */
{
.identifier = 0xd,
.cfg_ddr_rtp = 0x7,
.cfg_ddr_wtr = 0x7,
.cfg_ddr_rp = 0xd,
.cfg_ddr_rcd = 0xd,
.cfg_ddr_ras = 0x25,
.cfg_ddr_rrd = 0x7,
.cfg_ddr_rc = 0x34,
.cfg_ddr_mrd = 0x6,
.cfg_ddr_mod = 0xc,
.cfg_ddr_faw = 0x21,
.cfg_ddr_wlmrd = 0x28,
.cfg_ddr_wlo = 0x7,
.cfg_ddr_xp = 0x7,
.cfg_ddr_rfc = 0x118,
.cfg_ddr_xs = 0x200,
.cfg_ddr_dllk = 0x200,
.cfg_ddr_cke = 0x5,
.cfg_ddr_rtodt = 0x0,
.cfg_ddr_rtw = 0x7,
.cfg_ddr_refi = 0x4e,
.cfg_ddr_refi_mddr3 = 0x4,
.cfg_ddr_cl = 0xd,
.cfg_ddr_wr = 0x10,
.cfg_ddr_cwl = 0x9,
.cfg_ddr_al = 0x0,
.cfg_ddr_dqs = 0x17,
.cfg_ddr_cksre = 0xf,
.cfg_ddr_cksrx = 0xf,
.cfg_ddr_zqcs = 0x40,
.cfg_ddr_xpdll = 0x17,
.cfg_ddr_exsr = 0x200,
.cfg_ddr_zqcl = 0x88,
.cfg_ddr_zqcsi = 0x3e8,
.cfg_ddr_tccdl = 0x0,
.cfg_ddr_tdqsck = 0x0,
.cfg_ddr_tdqsckmax = 0x0,
.rsv_char = 0x0,
.rsv_int = 0x0,
},
/* "ddrt_" array index: 4 */
{
.identifier = 0xf,
.cfg_ddr_rtp = 0x4,
.cfg_ddr_wtr = 0x6,
.cfg_ddr_rp = 0xb,
.cfg_ddr_rcd = 0xb,
.cfg_ddr_ras = 0x23,
.cfg_ddr_rrd = 0x4,
.cfg_ddr_rc = 0x2e,
.cfg_ddr_mrd = 0x8,
.cfg_ddr_mod = 0x18,
.cfg_ddr_faw = 0x1c,
.cfg_ddr_wlmrd = 0x28,
.cfg_ddr_wlo = 0x8,
.cfg_ddr_xp = 0x7,
.cfg_ddr_rfc = 0x118,
.cfg_ddr_xs = 0x200,
.cfg_ddr_dllk = 0x400,
.cfg_ddr_cke = 0x5,
.cfg_ddr_rtodt = 0x0,
.cfg_ddr_rtw = 0x7,
.cfg_ddr_refi = 0x4e,
.cfg_ddr_refi_mddr3 = 0x4,
.cfg_ddr_cl = 0xb,
.cfg_ddr_wr = 0xd,
.cfg_ddr_cwl = 0xb,
.cfg_ddr_al = 0x0,
.cfg_ddr_dqs = 0x17,
.cfg_ddr_cksre = 0xf,
.cfg_ddr_cksrx = 0xf,
.cfg_ddr_zqcs = 0x80,
.cfg_ddr_xpdll = 0x17,
.cfg_ddr_exsr = 0x400,
.cfg_ddr_zqcl = 0x100,
.cfg_ddr_zqcsi = 0x3e8,
.cfg_ddr_tccdl = 0x5,
.cfg_ddr_tdqsck = 0x0,
.cfg_ddr_tdqsckmax = 0x0,
.rsv_char = 0x0,
.rsv_int = 0x0,
},
/* "ddrt_" array index: 5 */
{
.identifier = 0x12,
.cfg_ddr_rtp = 0x9,
.cfg_ddr_wtr = 0x9,
.cfg_ddr_rp = 0x12,
.cfg_ddr_rcd = 0x12,
.cfg_ddr_ras = 0x2a,
.cfg_ddr_rrd = 0x8,
.cfg_ddr_rc = 0x3c,
.cfg_ddr_mrd = 0x8,
.cfg_ddr_mod = 0x18,
.cfg_ddr_faw = 0x2a,
.cfg_ddr_wlmrd = 0x28,
.cfg_ddr_wlo = 0xb,
.cfg_ddr_xp = 0x7,
.cfg_ddr_rfc = 0x1a4,
.cfg_ddr_xs = 0x200,
.cfg_ddr_dllk = 0x400,
.cfg_ddr_cke = 0x5,
.cfg_ddr_rtodt = 0x0,
.cfg_ddr_rtw = 0x7,
.cfg_ddr_refi = 0x4e,
.cfg_ddr_refi_mddr3 = 0x4,
.cfg_ddr_cl = 0x12,
.cfg_ddr_wr = 0x12,
.cfg_ddr_cwl = 0xc,
.cfg_ddr_al = 0x0,
.cfg_ddr_dqs = 0x17,
.cfg_ddr_cksre = 0xf,
.cfg_ddr_cksrx = 0xf,
.cfg_ddr_zqcs = 0x80,
.cfg_ddr_xpdll = 0x17,
.cfg_ddr_exsr = 0x400,
.cfg_ddr_zqcl = 0x100,
.cfg_ddr_zqcsi = 0x3e8,
.cfg_ddr_tccdl = 0x6,
.cfg_ddr_tdqsck = 0x0,
.cfg_ddr_tdqsckmax = 0x0,
.rsv_char = 0x0,
.rsv_int = 0x0,
},
/* "ddrt_" array index: 6 */
{
.identifier = 0x3,
.cfg_ddr_rtp = 0x4,
.cfg_ddr_wtr = 0x6,
.cfg_ddr_rp = 0x12,
.cfg_ddr_rcd = 0x12,
.cfg_ddr_ras = 0x2a,
.cfg_ddr_rrd = 0x4,
.cfg_ddr_rc = 0x3c,
.cfg_ddr_mrd = 0x8,
.cfg_ddr_mod = 0x18,
.cfg_ddr_faw = 0x2a,
.cfg_ddr_wlmrd = 0x28,
.cfg_ddr_wlo = 0xb,
.cfg_ddr_xp = 0x7,
.cfg_ddr_rfc = 0x1a4,
.cfg_ddr_xs = 0x200,
.cfg_ddr_dllk = 0x400,
.cfg_ddr_cke = 0x5,
.cfg_ddr_rtodt = 0x0,
.cfg_ddr_rtw = 0x7,
.cfg_ddr_refi = 0x4e,
.cfg_ddr_refi_mddr3 = 0x4,
.cfg_ddr_cl = 0x12,
.cfg_ddr_wr = 0x12,
.cfg_ddr_cwl = 0xc,
.cfg_ddr_al = 0x0,
.cfg_ddr_dqs = 0x17,
.cfg_ddr_cksre = 0xf,
.cfg_ddr_cksrx = 0xf,
.cfg_ddr_zqcs = 0x80,
.cfg_ddr_xpdll = 0x17,
.cfg_ddr_exsr = 0x400,
.cfg_ddr_zqcl = 0x100,
.cfg_ddr_zqcsi = 0x3e8,
.cfg_ddr_tccdl = 0x6,
.cfg_ddr_tdqsck = 0x0,
.cfg_ddr_tdqsckmax = 0x0,
.rsv_char = 0x0,
.rsv_int = 0x0,
},
};
/* "pll__" structure */
pll_set_t __pll_setting = {
.cpu_clk = 0x4b0,
.pxp = 0x0,
.spi_ctrl = 0x0,
.vddee = 0x3e8,
.vcck = 0x460,
.lCustomerID = 0x0
.debug_mode = 0x0
.ddr_clk_debug = 0x0
.cpu_clk_debug = 0x0
.rsv_s1 = 0x0
.ddr_pll_ssc = 0x0
.rsv_i1 = 0x0
.rsv_l3 = 0x0
.rsv_l4 = 0x0
.rsv_l5 = 0x0
};My only remaning question is how do I effectively ship this for others? Thanks. PS: I can already tell that my work that I was about to commit to this repository doesn't seem correct as some of the values don't match up. |
Device specifications: https://whatismyphone.net/vendors/videostrong/km5-android-tv-box-km5
The manufacturer's website is here: https://www.videostrong.com/ (Unfortunately the original device page has been taken down)
This is a board that I've ripped the NAND module (usually has one) off of it so I can't rely on the original bootloader tricks to get a newer version on U-Boot running on it. Thankfully I was able to get it going by dumping and extracting the necessary bootloader parts from the original firmware dump I found somewhere and I've tested that it works.
The
acs.bindump is based on theddrs_tables found inbl2.bin, through crude hex editing I was able to transfer that over to the Le Potato'sacs.bin, I've tested that and it seems to work. The rest of the files are original from the device's ROM dump.