New project's for sequential logic

lab_06/src/01_counter_simple/synthesis/de10_lite.qsf

@@ -0,0 +1,60 @@
+set_global_assignment -name FAMILY "MAX 10"
+set_global_assignment -name DEVICE 10M50DAF484C7G
+set_global_assignment -name NUM_PARALLEL_PROCESSORS 4
+
+set_global_assignment -name TOP_LEVEL_ENTITY de10_lite
+
+set_global_assignment -name VERILOG_FILE de10_lite.v
+set_global_assignment -name VERILOG_FILE ../simple_counter.v
+set_global_assignment -name VERILOG_FILE ../../common/led7.v
+set_global_assignment -name VERILOG_FILE ../../common/clk_divider.v
+
+set_global_assignment -name SDC_FILE de10_lite.sdc
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK*
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX*
+set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY*
+
+#============================================================
+# CLOCK
+#============================================================
+set_location_assignment PIN_P11 -to CLOCK_50
+
+#============================================================
+# KEY
+#============================================================
+set_location_assignment PIN_B8 -to KEY[0]
+
+#============================================================
+# HEX0
+#============================================================
+
+set_location_assignment PIN_C14 -to HEX0[0]
+set_location_assignment PIN_E15 -to HEX0[1]
+set_location_assignment PIN_C15 -to HEX0[2]
+set_location_assignment PIN_C16 -to HEX0[3]
+set_location_assignment PIN_E16 -to HEX0[4]
+set_location_assignment PIN_D17 -to HEX0[5]
+set_location_assignment PIN_C17 -to HEX0[6]
+set_location_assignment PIN_D15 -to HEX0[7]
+
+#============================================================
+# HEX1
+#============================================================
+
+set_location_assignment PIN_C18 -to HEX1[0]
+set_location_assignment PIN_D18 -to HEX1[1]
+set_location_assignment PIN_E18 -to HEX1[2]
+set_location_assignment PIN_B16 -to HEX1[3]
+set_location_assignment PIN_A17 -to HEX1[4]
+set_location_assignment PIN_A18 -to HEX1[5]
+set_location_assignment PIN_B17 -to HEX1[6]
+set_location_assignment PIN_A16 -to HEX1[7]
+
+set_global_assignment -name LAST_QUARTUS_VERSION "16.1.2 Standard Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_file
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

lab_06/src/02_counter_with_load/synthesis/de2_115.sdc → lab_06/src/01_counter_simple/synthesis/de10_lite.sdc

@@ -2,6 +2,10 @@ create_clock -period 50MHz [get_ports CLOCK_50]
 
 derive_clock_uncertainty
 
+create_generated_clock -name clk_slow\
+                       -source [get_ports CLOCK_50]\
+                       [get_registers {clk_divider:clk_div|cnt_div[*]}]
+
 set_false_path -from * -to [get_ports {HEX0[*]}]
 set_false_path -from * -to [get_ports {HEX1[*]}]
 

lab_06/src/01_counter_simple/synthesis/de2_115.v → lab_06/src/01_counter_simple/synthesis/de10_lite.v

@@ -1,10 +1,10 @@
-module de2_115
+module de10_lite
 (
   input        CLOCK_50,
   input [0:0]  KEY,
 
-  output [6:0] HEX1,
-  output [6:0] HEX0
+  output [7:0] HEX1,
+  output [7:0] HEX0
 );
 
    localparam CNT_W = 8;

lab_06/src/02_counter_with_load/synthesis/de10_lite.qsf

@@ -0,0 +1,72 @@
+set_global_assignment -name FAMILY "MAX 10"
+set_global_assignment -name DEVICE 10M50DAF484C7G
+set_global_assignment -name NUM_PARALLEL_PROCESSORS 4
+
+set_global_assignment -name TOP_LEVEL_ENTITY de10_lite
+
+set_global_assignment -name VERILOG_FILE de10_lite.v
+set_global_assignment -name VERILOG_FILE ../cnt_load.v
+set_global_assignment -name VERILOG_FILE ../../common/led7.v
+set_global_assignment -name VERILOG_FILE ../../common/clk_divider.v
+
+set_global_assignment -name SDC_FILE de10_lite.sdc
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL"           -to CLOCK*
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL"           -to HEX*
+set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY*
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL"           -to SW*
+
+#============================================================
+# CLOCK
+#============================================================
+set_location_assignment PIN_P11 -to CLOCK_50
+
+#============================================================
+# KEY
+#============================================================
+set_location_assignment PIN_B8 -to KEY[0]
+set_location_assignment PIN_A7 -to KEY[1]
+
+#============================================================
+# HEX0
+#============================================================
+
+set_location_assignment PIN_C14 -to HEX0[0]
+set_location_assignment PIN_E15 -to HEX0[1]
+set_location_assignment PIN_C15 -to HEX0[2]
+set_location_assignment PIN_C16 -to HEX0[3]
+set_location_assignment PIN_E16 -to HEX0[4]
+set_location_assignment PIN_D17 -to HEX0[5]
+set_location_assignment PIN_C17 -to HEX0[6]
+set_location_assignment PIN_D15 -to HEX0[7]
+
+#============================================================
+# HEX1
+#============================================================
+
+set_location_assignment PIN_C18 -to HEX1[0]
+set_location_assignment PIN_D18 -to HEX1[1]
+set_location_assignment PIN_E18 -to HEX1[2]
+set_location_assignment PIN_B16 -to HEX1[3]
+set_location_assignment PIN_A17 -to HEX1[4]
+set_location_assignment PIN_A18 -to HEX1[5]
+set_location_assignment PIN_B17 -to HEX1[6]
+set_location_assignment PIN_A16 -to HEX1[7]
+
+#============================================================
+# SW
+#============================================================
+
+set_location_assignment PIN_C10 -to SW[0]
+set_location_assignment PIN_C11 -to SW[1]
+set_location_assignment PIN_D12 -to SW[2]
+set_location_assignment PIN_C12 -to SW[3]
+set_location_assignment PIN_A12 -to SW[4]
+set_location_assignment PIN_B12 -to SW[5]
+set_location_assignment PIN_A13 -to SW[6]
+set_location_assignment PIN_A14 -to SW[7]
+set_location_assignment PIN_B14 -to SW[8]
+set_location_assignment PIN_F15 -to SW[9]
+
+
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_file

lab_06/src/02_counter_with_load/synthesis/de10_lite.sdc

@@ -0,0 +1,11 @@
+create_clock -name clk50 -period 50MHz [get_ports CLOCK_50]
+derive_clock_uncertainty
+create_generated_clock -name clk_slow\
+                       -source [get_ports CLOCK_50]\
+                       [get_registers {clk_divider:clk_div|cnt_div[*]}]
+
+set_false_path -from * -to [get_ports {HEX0[*]}]
+set_false_path -from * -to [get_ports {HEX1[*]}]
+
+set_false_path -from [get_ports {KEY[*]}]  -to [all_clocks]
+set_false_path -from [get_ports {SW[*]} ]  -to [all_clocks]

lab_06/src/02_counter_with_load/synthesis/de2_115.v → lab_06/src/02_counter_with_load/synthesis/de10_lite.v

@@ -1,10 +1,10 @@
-module de2_115
+module de10_lite
   (
   input        CLOCK_50,
   input [1:0]  KEY,
   input [7:0]  SW,
-  output [6:0] HEX1,
-  output [6:0] HEX0
+  output [7:0] HEX1,
+  output [7:0] HEX0
 );
 
    localparam CNT_W = 8;