LDPC-Code-Decoder

Implementation of partly parallel LDPC code decoder in Verilog.

Architecture

Implemented the architecture proposed in this paper

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
CNU		CNU
PE_block		PE_block
Utilities		Utilities
VNU		VNU
address_generator		address_generator
data		data
memory		memory
permutations		permutations
.gitignore		.gitignore
Decoder.v		Decoder.v
Decoder_tb.v		Decoder_tb.v
LICENSE		LICENSE
README.md		README.md
example.py		example.py
verilog_decoder.py		verilog_decoder.py