mamba: avoid redundant HBM reloads in causal_conv1d_update shift loop#4460
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wdykas wants to merge 4 commits intoNVIDIA:mainfrom
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mamba: avoid redundant HBM reloads in causal_conv1d_update shift loop#4460wdykas wants to merge 4 commits intoNVIDIA:mainfrom
wdykas wants to merge 4 commits intoNVIDIA:mainfrom
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The original shift loop re-reads conv_state[1..WIDTH-1] from HBM on every sequence step, even though those same values are already in registers as x_val_0/1/2 from the earlier load. When state_len == WIDTH (the common Mamba configuration where the conv state depth equals the kernel width), skip the re-reads and store from the existing registers. The HAS_INT_STATE snapshot path benefits from the same reuse. state_len > WIDTH falls through to the original loop. Numerically bit-exact on conv_state; measured ~1.5% decode throughput improvement on nano-v3 at BS=1, OSL=256 (p50 245.21 -> 248.79 tok/s). Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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/ok to test 31fa060 |
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/ok to test e5c3fdc |
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/claude review |
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added 2 commits
April 28, 2026 06:58
…dykas/Megatron-LM into fix/causal-conv1d-shift-loop-hbm-reads
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/ok to test 48afcad |
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The original shift loop re-reads conv_state[1..WIDTH-1] from HBM on every sequence step, even though those same values are already in registers as x_val_0/1/2 from the earlier load. When state_len == WIDTH (the common Mamba configuration where the conv state depth equals the kernel width), skip the re-reads and store from the existing registers. The HAS_INT_STATE snapshot path benefits from the same reuse. state_len > WIDTH falls through to the original loop.
Numerically bit-exact on conv_state; measured ~1.5% decode throughput improvement on nano-v3 at BS=1, OSL=256 (p50 245.21 -> 248.79 tok/s).
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