Docs (dn): Geoffrey entry 2/13

src/design_notebooks/2024spring/gg2692.md

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+## Week of 2 February 2024
+
+Project Work:
+
+- [Onboarding Lab 1](https://github.com/geoffguin124/NYUProcDesignLabs): Completed Lab 1
+
+I spent this week working on Lab 1, and I didn't really have any issues with the lab, except for
+forgetting to save my VScode files. I will be continuing to work on the rest of the onboarding labs,
+aiming for getting 1-2 done per week.
+
+## Week of 18 February 2024
+
+Project Work:
+
+- [Onboarding Lab 2](https://github.com/geoffguin124/NYUProcDesignLabs): Completed Lab 2
+
+I spent this week finishing up Lab 2 and trying to familiarize myself with System Verilog. I have worked with VHDL before, so I kind of understand how SV works better than I would if I didn't use VHDL before. I also installed a System Verilog formatter, which makes coding in it a lot easier.
+
+## Week of 25 February 2024
+
+Project Work:
+
+- [Onboarding Lab 3](https://github.com/geoffguin124/NYUProcDesignLabs): Completed Lab 3
+
+This past 10 days I was working Labs 3 and 4. I just finished up Lab 3, linked in the link above. This lab was a bit confusing at first, but eventually I started to understand. I think this is a great way to understand the Cmake toolchain, especially since I didn't understand it too well intially. I want to practice understanding CMakeLists file more, I will do some more reading to understand that.
+
+## Week of March 3 2024
+
+Project Work:
+
+- [Onboarding Lab 3](https://github.com/geoffguin124/NYUProcDesignLabs): Completed onboarding labs
+
+This past week I have been working on finishing all of the onboarding labs, which can be linked to the above repo containing all of my onboarding labs. The onboarding labs have been relatively straightforward, the most confusing part definitely being the toolchain configuration and how all of these tools work together. The code has been decently challenging to write, considering the lack of a proper IDE for Verilog, so having to memorize the syntax/types has been necessary for doing the labs. I also had a poor understanding of what each tool actually did, so that messed with my projects a bit. I was intially writing tests in SV, while we were supposed to be doing it in C++. I thought that vertilator made the tests for you, while it just produces a verilated module for the user to use.
+
+## Week of March 23 2024
+
+Project Work:
+
+- [Documentation]
+
+Since a bit before and after spring break, I have been working on reading the documentation for the AMBA team. I am trying to figure out how to implement the memory suboordiate component, but this is proving to be a daunting task, as there is not a lot of material available through the internet. I am going to spend some more time with Rishyak trying to figure out this issue, and I am hoping that I will actually be able to write some code in the very near future. Also still reading up on docs on how SV and C++ work together through the Cmake toolchain with stuff like verilator.
+
+## Week of March 30 2024
+
+Project Work:
+
+- [AMBA Memory Suboordinate Design](https://github.com/NYU-Processor-Design/nyu-amba/pull/24): Started memory sub work
+
+This past week I have been working on implementing a general memory suboordinate for the AMBA team. I am currently working on implementing the behavioral model, however I am having some trouble on that. Will ask Rishyak this week for some help, but I think that I got all of the control,signals down. However, that is just kind of copy and pasting from the docs, so the behavioral component will be much harder to accurately implement.
+
+## Week of April 10 2024
+
+Project Work:
+
+- [AMBA Memory Suboordinate Design](https://github.com/NYU-Processor-Design/nyu-amba/pull/24): Initial design of memory sub done
+
+I was able to complete the memory sub work intially, however there are some issues with how I was interfacing with our current libraries, so I need to fix that. I am waiting for Rishyak to make a comment on my PR, and then I will continue with the work I am currently doing.
+
+## Week of April 17 2024
+
+Project Work:
+
+- [AMBA Memory Suboordinate Design](https://github.com/NYU-Processor-Design/nyu-amba/pull/24): Started memory sub work
+
+I integrated the AHBCommon_if and MemCommon_if interfaces into the SubMemCtrl module, replacing direct signal definitions with these interfaces. Also I added the ahb_resp_t enum for response status signaling within the module. I think that these changes will smooth out the process of creating the rest of the design.