Add AMDS IP Core changes to implement the DCP

ip_repo/amdc_amds_1.0/hdl/amdc_amds_v1_0.v

@@ -11,7 +11,7 @@
 
         // Parameters of Axi Slave Bus Interface S00_AXI
         parameter integer C_S00_AXI_DATA_WIDTH    = 32,
-        parameter integer C_S00_AXI_ADDR_WIDTH    = 6
+        parameter integer C_S00_AXI_ADDR_WIDTH    = 7
     )
     (
         // Users to add ports here

ip_repo/amdc_amds_1.0/src/adc_uart_rx.v

@@ -9,14 +9,23 @@ module adc_uart_rx(
 
     // The data line coming from the AMDS
     input wire din,
+    input wire [11:0] is_dout_enabled,
 
-    output wire [3:0] is_dout_valid, // is_dout_valid[0] == 1 implies that adc_dout0 is valid
+    output wire [11:0] is_dout_valid, // is_dout_valid[0] == 1 implies that adc_dout0 is valid
     output reg adc_uart_done,
     output reg assert_done,
     output reg [15:0] adc_dout0,
     output reg [15:0] adc_dout1,
     output reg [15:0] adc_dout2,
     output reg [15:0] adc_dout3,
+    output reg [15:0] adc_dout4,
+    output reg [15:0] adc_dout5,
+    output reg [15:0] adc_dout6,
+    output reg [15:0] adc_dout7,
+    output reg [15:0] adc_dout8,
+    output reg [15:0] adc_dout9,
+    output reg [15:0] adc_dout10,
+    output reg [15:0] adc_dout11,
 
     output reg [15:0] counter_bytes_valid,
     output reg [15:0] counter_bytes_corrupt,
@@ -30,13 +39,13 @@ module adc_uart_rx(
 reg rst_packet_counter;
 reg inc_packet_counter;
 
-reg [1:0] packet_counter;
+reg [11:0] packet_counter;
 
 always @(posedge clk, negedge rst_n) begin
     if (!rst_n)
-        packet_counter <= 2'b0;
+        packet_counter <= 12'b0;
     else if (rst_packet_counter)
-        packet_counter <= 2'b0;
+        packet_counter <= 12'b0;
     else if (inc_packet_counter)
         packet_counter <= packet_counter + 1;
 end
@@ -47,14 +56,17 @@ end
 
 reg is_dout0_valid, is_dout1_valid, is_dout2_valid, is_dout3_valid;
 
+reg is_dout4_valid, is_dout5_valid, is_dout6_valid, is_dout7_valid;
+reg is_dout8_valid, is_dout9_valid, is_dout10_valid, is_dout11_valid;
+
 reg assert_data_valid, clr_all_data_valid;
 
 always @(posedge clk, negedge rst_n) begin
     if (~rst_n)
         is_dout0_valid <= 1'b0;
     else if (clr_all_data_valid)
         is_dout0_valid <= 1'b0;
-    else if (assert_data_valid & packet_counter == 0)
+    else if (assert_data_valid & packet_counter == 0 & is_dout_enabled[0])
         is_dout0_valid <= 1'b1;
 end
 
@@ -63,7 +75,7 @@ always @(posedge clk, negedge rst_n) begin
         is_dout1_valid <= 1'b0;
     else if (clr_all_data_valid)
         is_dout1_valid <= 1'b0;
-    else if (assert_data_valid & packet_counter == 1)
+    else if (assert_data_valid & packet_counter == 1 & is_dout_enabled[1])
         is_dout1_valid <= 1'b1;
 end
 
@@ -72,7 +84,7 @@ always @(posedge clk, negedge rst_n) begin
         is_dout2_valid <= 1'b0;
     else if (clr_all_data_valid)
         is_dout2_valid <= 1'b0;
-    else if (assert_data_valid & packet_counter == 2)
+    else if (assert_data_valid & packet_counter == 2 & is_dout_enabled[2])
         is_dout2_valid <= 1'b1;
 end
 
@@ -81,12 +93,97 @@ always @(posedge clk, negedge rst_n) begin
         is_dout3_valid <= 1'b0;
     else if (clr_all_data_valid)
         is_dout3_valid <= 1'b0;
-    else if (assert_data_valid & packet_counter == 3)
+    else if (assert_data_valid & packet_counter == 3 & is_dout_enabled[3])
         is_dout3_valid <= 1'b1;
 end
 
+always @(posedge clk, negedge rst_n) begin
+    if (~rst_n)
+        is_dout4_valid <= 1'b0;
+    else if (clr_all_data_valid)
+        is_dout4_valid <= 1'b0;
+    else if (assert_data_valid & packet_counter == 4 & is_dout_enabled[4])
+        is_dout4_valid <= 1'b1;
+end
+
+always @(posedge clk, negedge rst_n) begin
+    if (~rst_n)
+        is_dout5_valid <= 1'b0;
+    else if (clr_all_data_valid)
+        is_dout5_valid <= 1'b0;
+    else if (assert_data_valid & packet_counter == 5 & is_dout_enabled[5])
+        is_dout5_valid <= 1'b1;
+end
+
+always @(posedge clk, negedge rst_n) begin
+    if (~rst_n)
+        is_dout6_valid <= 1'b0;
+    else if (clr_all_data_valid)
+        is_dout6_valid <= 1'b0;
+    else if (assert_data_valid & packet_counter == 6 & is_dout_enabled[6])
+        is_dout6_valid <= 1'b1;
+end
+
+always @(posedge clk, negedge rst_n) begin
+    if (~rst_n)
+        is_dout7_valid <= 1'b0;
+    else if (clr_all_data_valid)
+        is_dout7_valid <= 1'b0;
+    else if (assert_data_valid & packet_counter == 7 & is_dout_enabled[7])
+        is_dout7_valid <= 1'b1;
+end
+
+always @(posedge clk, negedge rst_n) begin
+    if (~rst_n)
+        is_dout8_valid <= 1'b0;
+    else if (clr_all_data_valid)
+        is_dout8_valid <= 1'b0;
+    else if (assert_data_valid & packet_counter == 8 & is_dout_enabled[8])
+        is_dout8_valid <= 1'b1;
+end
+
+always @(posedge clk, negedge rst_n) begin
+    if (~rst_n)
+        is_dout9_valid <= 1'b0;
+    else if (clr_all_data_valid)
+        is_dout9_valid <= 1'b0;
+    else if (assert_data_valid & packet_counter == 9 & is_dout_enabled[9])
+        is_dout9_valid <= 1'b1;
+end
+
+always @(posedge clk, negedge rst_n) begin
+    if (~rst_n)
+        is_dout10_valid <= 1'b0;
+    else if (clr_all_data_valid)
+        is_dout10_valid <= 1'b0;
+    else if (assert_data_valid & packet_counter == 10 & is_dout_enabled[10])
+        is_dout10_valid <= 1'b1;
+end
+
+always @(posedge clk, negedge rst_n) begin
+    if (~rst_n)
+        is_dout11_valid <= 1'b0;
+    else if (clr_all_data_valid)
+        is_dout11_valid <= 1'b0;
+    else if (assert_data_valid & packet_counter == 11 & is_dout_enabled[11])
+        is_dout11_valid <= 1'b1;
+end
+
 // Concatenate the individual valid registers into output bus
-assign is_dout_valid = {is_dout3_valid, is_dout2_valid, is_dout1_valid, is_dout0_valid};
+assign is_dout_valid = {
+    is_dout11_valid,
+    is_dout10_valid,
+    is_dout9_valid,
+    is_dout8_valid,
+    is_dout7_valid,
+    is_dout6_valid,
+    is_dout5_valid,
+    is_dout4_valid,
+    is_dout3_valid,
+    is_dout2_valid,
+    is_dout1_valid,
+    is_dout0_valid
+};
 
 
 // ===================
@@ -178,39 +275,47 @@ always @(posedge clk, negedge rst_n) begin
         adc_dout1 <= 16'b0;
         adc_dout2 <= 16'b0;
         adc_dout3 <= 16'b0;
+        adc_dout4 <= 16'b0;
+        adc_dout5 <= 16'b0;
+        adc_dout6 <= 16'b0;
+        adc_dout7 <= 16'b0;
+        adc_dout8 <= 16'b0;
+        adc_dout9 <= 16'b0;
+        adc_dout10 <= 16'b0;
+        adc_dout11 <= 16'b0;
     end
 
     else if (load_doutN_LSB) begin
         case (packet_counter)
-            4'd0: begin
-                adc_dout0[7:0] <= uart_data_byte;
-            end
-            4'd1: begin
-                adc_dout1[7:0] <= uart_data_byte;
-            end
-            4'd2: begin
-                adc_dout2[7:0] <= uart_data_byte;
-            end
-            4'd3: begin
-                adc_dout3[7:0] <= uart_data_byte;
-            end
+            4'd0:  adc_dout0[7:0]  <= uart_data_byte;
+            4'd1:  adc_dout1[7:0]  <= uart_data_byte;
+            4'd2:  adc_dout2[7:0]  <= uart_data_byte;
+            4'd3:  adc_dout3[7:0]  <= uart_data_byte;
+            4'd4:  adc_dout4[7:0]  <= uart_data_byte;
+            4'd5:  adc_dout5[7:0]  <= uart_data_byte;
+            4'd6:  adc_dout6[7:0]  <= uart_data_byte;
+            4'd7:  adc_dout7[7:0]  <= uart_data_byte;
+            4'd8:  adc_dout8[7:0]  <= uart_data_byte;
+            4'd9:  adc_dout9[7:0]  <= uart_data_byte;
+            4'd10: adc_dout10[7:0] <= uart_data_byte;
+            4'd11: adc_dout11[7:0] <= uart_data_byte;
         endcase
     end
 
     else if (load_doutN_MSB) begin
         case (packet_counter)
-            4'd0: begin
-                adc_dout0[15:8] <= uart_data_byte;
-            end
-            4'd1: begin
-                adc_dout1[15:8] <= uart_data_byte;
-            end
-            4'd2: begin
-                adc_dout2[15:8] <= uart_data_byte;
-            end
-            4'd3: begin
-                adc_dout3[15:8] <= uart_data_byte;
-            end
+            4'd0:  adc_dout0[15:8]  <= uart_data_byte;
+            4'd1:  adc_dout1[15:8]  <= uart_data_byte;
+            4'd2:  adc_dout2[15:8]  <= uart_data_byte;
+            4'd3:  adc_dout3[15:8]  <= uart_data_byte;
+            4'd4:  adc_dout4[15:8]  <= uart_data_byte;
+            4'd5:  adc_dout5[15:8]  <= uart_data_byte;
+            4'd6:  adc_dout6[15:8]  <= uart_data_byte;
+            4'd7:  adc_dout7[15:8]  <= uart_data_byte;
+            4'd8:  adc_dout8[15:8]  <= uart_data_byte;
+            4'd9:  adc_dout9[15:8]  <= uart_data_byte;
+            4'd10: adc_dout10[15:8] <= uart_data_byte;
+            4'd11: adc_dout11[15:8] <= uart_data_byte;
         endcase
     end
 end
@@ -417,7 +522,7 @@ always @(*) begin
                 assert_data_valid = 1;
             end
 
-            if (packet_counter == 4'd3) begin
+            if (packet_counter == 12'd11 || (is_dout_enabled >> (packet_counter + 1)) == 0) begin
                 // Done (for real)! Captured all 4 data packets, so assert done and return to idle
                 next_state = `SM_IDLE;
                 assert_done = 1;

ip_repo/amdc_amds_1.0/xgui/amdc_amds_v2_0.tcl

@@ -0,0 +1,62 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  set C_S00_AXI_DATA_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox]
+  set_property tooltip {Width of S_AXI data bus} ${C_S00_AXI_DATA_WIDTH}
+  set C_S00_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}]
+  set_property tooltip {Width of S_AXI address bus} ${C_S00_AXI_ADDR_WIDTH}
+  ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
+	# Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
+	# Procedure called to validate C_S00_AXI_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
+	# Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
+	# Procedure called to validate C_S00_AXI_ADDR_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
+	# Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
+	# Procedure called to validate C_S00_AXI_BASEADDR
+	return true
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
+	# Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
+	# Procedure called to validate C_S00_AXI_HIGHADDR
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH}
+}
+

scripts/test.py

@@ -0,0 +1,19 @@
+from AMDC import AMDC
+
+amdc = AMDC()
+
+# Set comm defaults for ETHERNET
+amdc.setup_comm_defaults('eth')
+
+# Init ethernet 
+amdc.eth_init()
+
+# Set up the default ASCII command socket
+s0, s0_id = amdc.eth_new_socket('ascii_cmd')
+amdc.eth_set_default_ascii_cmd_socket(s0)
+
+amdc.connect()
+amdc.comm_cmd_delay_cmd = .01
+amdc.cmd('ctrl get enc')
+amdc.cmd('test analog')
+amdc.disconnect()

sdk/app_cpu1/.project

@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>app_cpu1</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+	</buildSpec>
+	<natures>
+	</natures>
+</projectDescription>