Pinned Loading

1. sc-bl sc-bl Public

   Forked from syntacore/sc-bl

   Syntacore first stage bootloader

   C 1

2. scr1 scr1 Public

   Forked from syntacore/scr1

   SCR1 is a high-quality open-source RISC-V MCU core in Verilog

   SystemVerilog 1

3. fpga-sdk-prj fpga-sdk-prj Public

   Forked from syntacore/fpga-sdk-prj

   FPGA-based SDK projects for SCRx cores

   Verilog

4. scr1_tang_primer20k scr1_tang_primer20k Public

   SystemVerilog

5. systemverilog-homework systemverilog-homework Public

   Forked from chipdesignschool/systemverilog-homework

   SystemVerilog language-oriented exercises

   SystemVerilog

6. Impulse2025_interconnect Impulse2025_interconnect Public

   SystemVerilog