fpga: $VERILOG_DEFINES and $YOSYS_ARGS passed to Yosys #117
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The ASIC flow has config.json that a user can provide but Yosys can also need globals options, particularly with Verilog pre-processor defines so the Verilog source can be shared between ASIC and FPGA allowing for example ASIC/FPGA target specific cells to be added/removed from design.
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The ASIC flow has config.json that a user can provide but Yosys can also need globals options, particularly with Verilog pre-processor defines so the Verilog source can be shared between ASIC and FPGA allowing for example ASIC/FPGA target specific cells to be added/removed from design.
This commit is still undergoing QA / testing on my side, will update here when done.