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mihir_task 1 - instantiated instruction decoder in top.v - #25

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TheDeepestSpace merged 9 commits into
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11-integrate-instruction-decode-with-memory-access
Jul 21, 2025
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mihir_task 1 - instantiated instruction decoder in top.v#25
TheDeepestSpace merged 9 commits into
mainfrom
11-integrate-instruction-decode-with-memory-access

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@MM871

@MM871 MM871 commented Mar 30, 2025

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@MM871 MM871 linked an issue Mar 30, 2025 that may be closed by this pull request
@joon2022park

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Instantiate 3 modules

(Use Boris's top.v as a baseline/reference)

  • ID stage (Instruction Decode)
  • MA stage (Memory access stage)

instantiated MA and ID
@MM871

MM871 commented Jun 9, 2025

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commited new changed regarding instantiating the ID and MA

instantiated in bottom of top.v and created the module in a seperate file Mux.v
@TheDeepestSpace

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Currently, it seems like we generally prefer case statements over dedicated modules for implementing muxes.

For instance in this commit for beq implementation we scraped the dedicated generic mux module in favour of case statement: ac38f59

@TheDeepestSpace

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hey @MM871, I just merged master into you branch and resolved all conflicts; i think we are missing a couple of variables there (see this job output -- https://github.com/UTOSS/risc-v/actions/runs/16403567149/job/46346493415?pr=25)

great job on using the case statements, you nailed it!

@TheDeepestSpace

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I just threw in the missing registers and it all compiles now! Thanks @MM871, gonna merge this now

@TheDeepestSpace
TheDeepestSpace merged commit 7949b9b into main Jul 21, 2025
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TheDeepestSpace deleted the 11-integrate-instruction-decode-with-memory-access branch May 7, 2026 02:35
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Integrate Top Level Module

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