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AIE profile fixes and re-formatting #7832

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merged 9 commits into from
Dec 8, 2023

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pgschuey
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@pgschuey pgschuey commented Dec 5, 2023

Problem solved by the commit

  • DMA-only tiles are not included when profiling memory modules
  • Corrected formatting in some files

How problem was solved, alternative solutions (if any) and why they were rejected
Include DMA-only tiles when appropriate

Risks (if any) associated the changes in the commit
It's only as good as the metadata quality

What has been tested and how, request additional testing if necessary
Tested on vck190

Documentation impact (if any)
DMA-only tiles are getting profiled

Paul Schumacher added 3 commits December 5, 2023 09:06
Signed-off-by: Paul Schumacher <[email protected]>
Signed-off-by: Paul Schumacher <[email protected]>
Signed-off-by: Paul Schumacher <[email protected]>
@pgschuey pgschuey requested a review from jvillarre as a code owner December 5, 2023 21:36
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gbuildx commented Dec 6, 2023

Build Passed!

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gbuildx commented Dec 8, 2023

Build Passed!

Paul Schumacher added 2 commits December 8, 2023 08:57
Signed-off-by: Paul Schumacher <[email protected]>
Signed-off-by: Paul Schumacher <[email protected]>
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gbuildx commented Dec 8, 2023

Build Passed!

@jvillarre jvillarre merged commit 1b076c4 into Xilinx:master Dec 8, 2023
@pgschuey pgschuey deleted the aie_profile_fixes branch March 5, 2024 18:23
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3 participants