VITIS-15146: Add GMIO-to-DDR connectivity support#9640
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stsoe merged 13 commits intoXilinx:masterfrom Mar 16, 2026
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clang-tidy review says "All clean, LGTM! 👍" |
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clang-tidy review says "All clean, LGTM! 👍" |
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Mar 3, 2026
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clang-tidy review says "All clean, LGTM! 👍" |
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clang-tidy review says "All clean, LGTM! 👍" |
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clang-tidy review says "All clean, LGTM! 👍" |
chvamshi-xilinx
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Mar 12, 2026
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Idea looks good overall, but there are some minor issues with current implementation.
Please review and fix.
added 12 commits
March 16, 2026 10:43
Signed-off-by: Bikash Singha <bisingha@xcobisingha50x.amd.com>
Signed-off-by: Bikash Singha <bisingha@xcobisingha50x.amd.com>
Signed-off-by: Bikash Singha <bisingha@xcobisingha50x.amd.com>
Signed-off-by: Bikash Singha <bisingha@xcobisingha50x.amd.com>
Signed-off-by: Bikash Singha <bisingha@xcobisingha50x.amd.com>
Signed-off-by: Bikash Singha <bisingha@xcobisingha50x.amd.com>
Signed-off-by: Bikash Singha <bisingha@xcobisingha50x.amd.com>
…e in all xclbins Signed-off-by: Bikash Singha <bisingha@xcobisingha50x.amd.com>
Signed-off-by: Bikash Singha <bisingha@xcobisingha50x.amd.com>
Signed-off-by: Bikash Singha <bisingha@xcobisingha50x.amd.com>
Signed-off-by: Bikash Singha <bisingha@xcobisingha50x.amd.com>
…connectivity Signed-off-by: Bikash Singha <bisingha@xcobisingha50x.amd.com>
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clang-tidy review says "All clean, LGTM! 👍" |
Signed-off-by: Bikash Singha <bisingha@xcobisingha50x.amd.com>
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clang-tidy review says "All clean, LGTM! 👍" |
stsoe
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Looks good, thanks for keeping xrt::xclbin implementation code simple.
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Revert Xilinx#9640 exception in kernel construction. Message blocks xclbins used by model-tests. Signed-off-by: Soren Soe <2106410+stsoe@users.noreply.github.com>
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Revert #9640 exception in kernel construction. Message blocks xclbins used by model-tests. Signed-off-by: Soren Soe <2106410+stsoe@users.noreply.github.com>
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Problem solved by the commit
It's a new feature. Adds APIs to resolve GMIO port names to memory bank indices so host code can allocate buffers in the correct DDR banks for AIE GMIOs. So it removes the hardcoding from all the host applications.
NOTE: This pr assumes all the xclbins will have IP_LAYOUT section irrespective of the type (non-aie, overlay aie, aie only, etc.)
API signature and Usage:
auto ghdl=xrt::graph(hwctx_1,"graphName");uint32_t bank_in_id = ghdl.gmio_bank_id("logicalGMIOName");auto din_buffer = xrt::aie::bo (hwctx_1, BLOCK_SIZE_in_Bytes,xrt::bo::flags::normal, bank_in_id);Bug / issue (if any) fixed, which PR introduced the bug, how it was discovered
It's not a bug but a new feature.
How problem was solved, alternative solutions (if any) and why they were rejected
It was solved by mapping the GMIO ports to its memory banks and assigning a mem index for buffer allocation. This happens just after loading the xclbin. And host can get the assigned bank id for a particular GMIO.
Risks (if any) associated the changes in the commit
n/a
What has been tested and how, request additional testing if necessary
Tested by having multiple usecases:
Documentation impact (if any)
Yes. The new API to get the memory bank id for a respective GMIO has to be logged.