[AIE] Legalize G_AND for <8 x s64> vector. #262
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SagarMaheshwari99
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| @@ -255,6 +255,13 @@ AIE2PLegalizerInfo::AIE2PLegalizerInfo(const AIE2PSubtarget &ST) | |||
| getActionDefinitionsBuilder({G_AND, G_OR}) | |||
| .legalFor({S32}) | |||
| .legalFor(AIE2PVectorTypes) | |||
| .bitcastIf( | |||
| [=](const LegalityQuery &Query) { | |||
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Make this more generic and also handle 256/1024 bit vectors?
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| @@ -305,7 +299,7 @@ AIE2PLegalizerInfo::AIE2PLegalizerInfo(const AIE2PSubtarget &ST) | |||
| .legalFor({V16S32, V32S16, V64S8}) | |||
| .widenScalarToNextPow2(0) | |||
| .clampScalar(0, S32, S32) | |||
| // AIE ISA supports only 512-bit vector add/sub/xor | |||
| // AIE ISA supports only 512-bit vector add/sub/xor/and/or | |||
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nit: why do we need to update the comment with "and/or"?
| @@ -1092,6 +1092,15 @@ def : PatInaccessibleMem<(int_aie2_v16bf16_to_v16i32 VEC256:$src, mSs:$shft), | |||
| def : PatInaccessibleMem<(int_aie2_clr16f_conf), | |||
| (VCLR_vclr_BF)>; | |||
|
|
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| // AIE does not have a native xor instruction for vector operands. | |||
| // Res = A xor B --> Res = AB' || A'B | |||
| foreach Ty = [v64i8, v32i16, v16i32] in { | |||
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Can it be shared between aie2 and aie2p? I see we have exactly the same implementation for aie2p.
| (v32i16 (REG_SEQUENCE VEC512, VEC256:$src2, sub_256_lo))), | ||
| sub_256_lo))>; | ||
| } | ||
| // VBOR / VBAND / XOR |
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nit: we don't have xor here
| // like scalarization. We can use G_CONCAT_VECTORS and unmerge to do this | ||
| // more optimally. | ||
| .customIf(vectorSmallerThan(0, 512)) | ||
| .bitcastIf(typeInSet(0, {AccV4S64, AccV8S64, AccV16S64}), |
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Why is it not for all aie2p accumulator types defined in AIE2PAccumulatorTypes?
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