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Merged
merged 254 commits into from
Mar 14, 2025
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b3909f4
[MLIR] Drop assumption of a surrounding builtin.func in promoteIfSing…
bondhugula Nov 23, 2024
4a0b8c3
[MLIR][Affine] Drop assumptions of surrounding builtin.func op in Uti…
bondhugula Nov 23, 2024
be75020
[MLIR] Fix unchecked use of memref memory space attr in affine data c…
bondhugula Nov 23, 2024
132de3a
[MLIR] Fix arbitrary checks in affine LICM (#116469)
bondhugula Nov 23, 2024
d1cca31
AMDGPU: Add v_permlane16_swap_b32 and v_permlane32_swap_b32 for gfx95…
arsenm Nov 23, 2024
33c2b20
AMDGPU: Define new sched model for gfx950 (#117261)
arsenm Nov 23, 2024
b078b88
AMDGPU: Handle gfx950 change in mfma_f64_16x16x4 + valu hazard (#117262)
arsenm Nov 23, 2024
8cb6c99
AMDGPU: Handle gfx950 XDL-write-overlapped-smfma-src-c wait state cha…
arsenm Nov 23, 2024
db08d78
AMDGPU: Handle v_mfma_f64_16x16x4_f64 srcc write VGPR hazard change f…
arsenm Nov 23, 2024
85601fd
AMDGPU: Handle v_mfma_f64_16x16x4_f64 write VGPR read srca/srcb hazar…
arsenm Nov 23, 2024
9d8a11f
[memprof] Remove verifyIndexedMemProfRecord and verifyFunctionProfile…
kazutakahirata Nov 23, 2024
68f7b07
[BasicBlockSections] Allow mixing of -basic-block-sections with MFS. …
rlavaee Nov 23, 2024
19ddafa
[llvm] Fix ObjectSizeOffsetVisitor behavior in exact mode upon negati…
serge-sans-paille Nov 23, 2024
3a31427
[Clang] Add C++26 approved in the Poland WG21 meeting
cor3ntin Nov 23, 2024
dbb21df
[X86] vector-shuffle-avx512.ll - regenerate TERNLOG comments
RKSimon Nov 23, 2024
1e31a45
[X86] lowerShuffleWithPERMV - commute VPERMV3 shuffles so any load is…
RKSimon Nov 23, 2024
5909139
[VPlan] Simplify and unify code in verifyEVLRecipe using all_of. (NFCI)
fhahn Nov 23, 2024
08e6566
[mlir][Func] Support 1:N result type conversions in `func.call` conve…
matthias-springer Nov 23, 2024
4a8329c
[libc++] Granularize <mutex> includes (#117068)
philnik777 Nov 23, 2024
aaa0dd2
[libc++][NFC] Remove a bunch of unused environment variables from the…
philnik777 Nov 23, 2024
56feea7
[mlir][python] Update minimal version of pybind11 to 2.10. (#117314)
ingomueller-net Nov 23, 2024
01e7564
[mlir] Add FileRange location type. (#80213)
jpienaar Nov 23, 2024
aa2d084
[clang-format][NFC] Reformat testcases added in 0ff8b7916050
owenca Nov 23, 2024
70bd80d
[X86] combineTargetShuffle - commute VPERMV3 shuffles so any load is …
RKSimon Nov 23, 2024
b0e7383
Reapply [flang][OpenMP] Avoid early returns, NFC #117231 (#117325)
kparzysz Nov 23, 2024
d3ce069
[AArch64][GlobalISel] Legalize ptr shuffle vector to s64 (#116013)
davemgreen Nov 23, 2024
2f69f9a
AMDGPU: Stop running assembler tests with default cpu (#117421)
arsenm Nov 23, 2024
8b087d6
AMDGPU: Move default wavesize hack for disassembler (#117422)
arsenm Nov 23, 2024
cd20fc0
AMDGPU: Remove wavefrontsize64 feature from dummy target (#117410)
arsenm Nov 23, 2024
1944d19
AMDGPU: Use isWave[32|64] instead of comparing size value (#117411)
arsenm Nov 23, 2024
94bde8c
[HLSL] Add `Increment`/`DecrementCounter` methods to structured buffe…
hekota Nov 23, 2024
b336310
[UTC] Add support for Xtensa (#117441)
s-barannikov Nov 23, 2024
14b9ca3
[Sema] Fix a warning
kazutakahirata Nov 23, 2024
5f9db08
Allow SymbolUserOpInterface operators to be used in RemoveDeadValues …
codemzs Nov 23, 2024
28064bf
[AArch64][GlobalISel] Update and cleanup a number of gisel tests. NFC
davemgreen Nov 23, 2024
e2519b6
[VPlan] Print incoming VPBB for Phi VPIRInstruction (NFC).
fhahn Nov 23, 2024
c8b837a
[MLIR][Python] Add the `--mlir-print-ir-tree-dir` to the C and Python…
joker-eph Nov 23, 2024
213b849
[RISCV][GISel] Use libcalls for some FP instructions when F/D aren't …
topperc Nov 23, 2024
dc4c8de
Revert "[HLSL] Add `Increment`/`DecrementCounter` methods to structur…
hekota Nov 23, 2024
3cecf17
[ELF] Refactor merge-* tests
MaskRay Nov 23, 2024
43e3871
[ELF] Make section member orders consistent
MaskRay Nov 23, 2024
d6e6478
[memprof] Remove a dead constructor in AllocationInfo (NFC) (#117427)
kazutakahirata Nov 23, 2024
d4bed61
[ELF] -r: keep sh_entsize for SHF_MERGE sections with relocations
MaskRay Nov 23, 2024
a5af621
[ELF] Make SyntheticSection parameter order match InputSection
MaskRay Nov 23, 2024
099a52f
[ELF] Reorder SectionBase/InputSectionBase members
MaskRay Nov 24, 2024
cf9b428
[ARC] Fix ARCISD::BRcc description (#117454)
s-barannikov Nov 24, 2024
afae1a5
[libc++] Remove _LIBCPP_DISABLE_AVAILABILITY macro (#112952)
ldionne Nov 24, 2024
042a1cc
[VPlan] Generalize type inference for binary/cast/shift/logic. NFC (#…
LiqinWeng Nov 24, 2024
e4e5206
[ELF] Make OutputDesc unique_ptr
MaskRay Nov 24, 2024
48b13ca
[RISCV][CostModel] cost of vector cttz/ctlz under ZVBB (#115800)
LiqinWeng Nov 24, 2024
a87f776
[ELF] Avoid make in elf::writeARMCmseImportLib
MaskRay Nov 24, 2024
c894d3a
Fixup a test for #116330, to make `REQUIRES:asserts`
chapuni Nov 24, 2024
ed1d90c
[clang][NFC] simplify the unset check in `ParseLabeledStatement` (#11…
HerrCai0907 Nov 24, 2024
a0ef12c
[mlir][LLVM] `LLVMTypeConverter`: Tighten materialization checks (#11…
matthias-springer Nov 24, 2024
1a2cc2b
[ELF] Exclude sizeof(InputSection) to _WIN32
MaskRay Nov 24, 2024
ae01e3a
[nfc][sancov] Remove unnecessary default argument (#117463)
vitalybuka Nov 24, 2024
215f3dd
[nfc][sancov] Remove unnecessary default argument (#117464)
vitalybuka Nov 24, 2024
8d65073
[AMDGPU] Fix AMDGPUISD::TRAP description (#117453)
s-barannikov Nov 24, 2024
c85c77c
[AVR] Fix shift node descriptions (#117456)
s-barannikov Nov 24, 2024
68a48ec
[clang][analysis][NFC]place the comment to correct position (#117467)
HerrCai0907 Nov 24, 2024
eb4d2f2
[ELF] Simplify reportMissingFeature. NFC
MaskRay Nov 24, 2024
5fa0345
[tsan] Unwind for CHECK according to fast_unwind_on_fatal (#117470)
vitalybuka Nov 24, 2024
4d4a353
[TSan] Increase the number of simultaneously locked mutexes that a th…
gbMattN Nov 24, 2024
2af6ddb
[mlir][ods] Fix missing property elision for variadic segment propert…
Moxinilian Nov 24, 2024
bd7d6c8
[bazel] Port 776476c282bca71d5b856e80e0a88fbd6f3ccdd2
d0k Nov 24, 2024
c4d656a
[bazel] Add missing dependencies for a0ef12c64284abf59bc092b2535cce12…
d0k Nov 24, 2024
f942949
[LLD][COFF] Require explicit specification of ARM64EC target (#116281)
cjacek Nov 24, 2024
0c21ed4
[clang-tidy][NFC] fix release note order (#117484)
HerrCai0907 Nov 24, 2024
7498eaa
[mlir][LLVM] Add the `ConvertToLLVMAttrInterface` and `ConvertToLLVMO…
fabianmcg Nov 24, 2024
08bf901
Revert "[AIX] Fix AIX BuildBot failure as AIX linker doesn't support …
xingxue-ibm Nov 24, 2024
63d9ef5
[AST] Migrate away from PointerUnion::{is,get} (NFC) (#117469)
kazutakahirata Nov 24, 2024
aafe934
[hexagon] Require "asserts" build for widen-not-load test (#117414)
androm3da Nov 24, 2024
6cfaddf
[X86] Split rr/rm CVT schedules on SNB/HSW/BDW (#117494)
RKSimon Nov 24, 2024
0a6d797
[X86] Improve F16C CVT schedules on SNB/HSW/BDW
RKSimon Nov 24, 2024
ff97b28
[ELF] Simplif reportUndefinedSymbol. NFC
MaskRay Nov 24, 2024
c2ffb42
[lldb] Fix TestLoadUnload.py (#117416)
splhack Nov 24, 2024
0dbdc6d
[VPlan] Simplify code to re-use existing basic blocks (NFCI).
fhahn Nov 24, 2024
d8495ed
[ELF] Change getLocation to use ELFSyncStream. NFC
MaskRay Nov 24, 2024
360718f
[test] Improve symbol-location.s to check --defsym
MaskRay Nov 24, 2024
c790d6f
[ELF] isCompatile: avoid a toStr and 2 ErrAlways
MaskRay Nov 24, 2024
c4dc5ed
[ELF] Avoid some toStr and ErrAlways
MaskRay Nov 24, 2024
1cd6275
[ELF] Remove unneeded Twine in ELFSyncStream
MaskRay Nov 24, 2024
590f451
[VPlan] Allow setting IR name for VPDerivedIVRecipe (NFCI).
fhahn Nov 24, 2024
5ce4d4c
[mlir] fix memory effects in GPU barrier elimination (#117432)
ftynse Nov 24, 2024
e3aafe4
[clang-tidy] fix false positive use-internal-linkage for func decl wi…
HerrCai0907 Nov 24, 2024
ae20dbd
[clang][analysis] refactor the unevaluated api (#117474)
HerrCai0907 Nov 24, 2024
605b8da
[clang-tidy] Fix false positive in cppcoreguidelines-avoid-const-or-r…
HerrCai0907 Nov 24, 2024
3c344f9
[clang][tablegen][NFC]add static for internal linkage function (#117479)
HerrCai0907 Nov 24, 2024
cbdd14e
[clang][NFC]add static for internal linkage function (#117482)
HerrCai0907 Nov 24, 2024
2a5e3a6
[AST] Fix a warning
kazutakahirata Nov 25, 2024
095f489
[X86] Swap ports 10 and 11 in SapphireRapids Scheduling Model (#117468)
boomanaiden154 Nov 25, 2024
512dc5c
[X86] Swap ports 10 and 11 in Alder Lake Scheduling Model (#117466)
boomanaiden154 Nov 25, 2024
5ed09d5
[Support] Check zstd decompress result before msan unpoison (#117276)
yingcong-wu Nov 25, 2024
6aeffa1
[ELF] --reproduce: strip directories for --dependency-file=
MaskRay Nov 25, 2024
e70f9e2
[LoongArch] Remove the added in #116762
SixWeining Nov 25, 2024
02408d6
[VP] Refactoring some functions in ExpandVectorPredication.NFC (#115840)
LiqinWeng Nov 25, 2024
5f3eab9
[AVR] Remove extra ROL / ROR operands (#117510)
s-barannikov Nov 25, 2024
bb5bbe5
[RISCV][GISel] Support s32/s64 G_FSUB/FDIV/FNEG without F/D extensions.
topperc Nov 23, 2024
345ca6a
[mlir][Transforms] Dialect conversion: extra signature conversion che…
matthias-springer Nov 25, 2024
0bfc951
[lldb] Remove lldbutil.get_stack_frames (NFC) (#117505)
kastiglione Nov 25, 2024
e26af09
[llvm] Add `BasicTTIImpl::areInlineCompatible` for target feature sub…
heiher Nov 25, 2024
3fb0bea
[RISCV][GISel] Add register class to some isel output patterns so the…
topperc Nov 25, 2024
2523439
[LoongArch] Add a test case for inline compatibility checks (#117144)
heiher Nov 25, 2024
7317a6e
[RISCV][MachineVerifier] Use RegUnit for register liveness checking (…
BeMg Nov 25, 2024
87cc4b4
[NFC] Fix buildbot fail by add riscv64-registered-target
BeMg Nov 25, 2024
9e3215a
[memprof] Add an assert to InstrProfWriter::addMemProfData (#117426)
kazutakahirata Nov 25, 2024
ff7b42c
[memprof] Speed up llvm-profdata (#117446)
kazutakahirata Nov 25, 2024
73bebf9
[LangRef] Update the position of some parameters in the vp intrinsic …
LiqinWeng Nov 25, 2024
b9731a4
[clang-format][doc] Minor cleanup
owenca Nov 25, 2024
2568e52
[X86,SimplifyCFG] Support hoisting load/store with conditional faulti…
phoebewang Nov 25, 2024
b0bdbf4
[mlir][bazel] Port https://github.com/llvm/llvm-project/commit/7498ea…
chsigg Nov 25, 2024
2585b6e
[mlir][bazel] Fix layering check failure.
chsigg Nov 25, 2024
df335b0
[Clang] Preserve partially substituted pack indexing type/expressions…
zyn0217 Nov 25, 2024
404d0e9
[mlir] Adjust code flagged by ClangTidyPerformance (NFC).
akuegel Nov 25, 2024
0fe12a7
[clang-format][NFC] Remove a pointer in ContinuationIndenter
owenca Nov 25, 2024
815a1bb
[SystemZ] Use getSignedConstant() where necessary (#117181)
nikic Nov 25, 2024
3317c9c
[AMDGPU] Use getSignedConstant() where necessary (#117328)
nikic Nov 25, 2024
55f5d68
[win/asan] Recognize mov QWORD PTR [rip + X], reg (#117335)
zmodem Nov 25, 2024
6512e48
[LLD][ARM] Allow R_ARM_SBREL32 relocations in debug info (#116956)
ostannard Nov 25, 2024
1bc9895
[lldb/DWARF] Remove duplicate type filtering (#116989)
labath Nov 25, 2024
866755f
[LLVM] Update backend maintainer (#116622)
nikic Nov 25, 2024
d35098b
[mlir][LLVM][NFC] Move `LLVMStructType` to ODS (#117485)
zero9178 Nov 25, 2024
2b5e2d7
[AArch64][GlobalISel] Extend arm64-vshift.ll test coverage. NFC
davemgreen Nov 25, 2024
7d8d51e
Recommit "[TargetVersion] Only enable on RISC-V and AArch64" (#117110…
BeMg Nov 25, 2024
e5faeb6
[InstCombine] Support reassoc for foldLogicOfFCmps (#116065)
nikic Nov 25, 2024
22ec44f
[DAGCombiner] Add support for scalarising extracts of a vector setcc …
david-arm Nov 25, 2024
321fe74
[InstCombine] Add extra test for eq of parts fold (NFC)
nikic Nov 25, 2024
db14010
[RISCV][TTI] Implement cost of intrinsic abs with LMUL (#115813)
LiqinWeng Nov 25, 2024
84fec77
[lldb][docs] Clarify unit for SVE P register size
DavidSpickett Nov 25, 2024
c537c75
[AArch64][GlobalISel] Scalarize i128 vector sadd_sat/uadd_sat/etc.
davemgreen Nov 25, 2024
f81f47e
[InstCombine] Add fptrunc of max test (NFC)
nikic Nov 25, 2024
15fadeb
[RISCV] Add cost for @llvm.experimental.vp.splat (#117313)
lukel97 Nov 25, 2024
48ec59c
[llvm][AMDGPU] Fold `llvm.amdgcn.wavefrontsize` early (#114481)
AlexVlx Nov 25, 2024
612f8ec
seq_cst is allowed in Flush since OpenMP 5.1. (#114072)
ShashwathiNavada Nov 25, 2024
e477989
[InstCombine] Handle trunc i1 pattern in eq-of-parts fold (#112704)
nikic Nov 25, 2024
ceaf6e9
[clang][bytecode] Support ImplicitValueInitExpr for multi-dim arrays …
tbaederr Nov 25, 2024
5352478
[TableGen] Remove comments from generated validateOperandClass (#117352)
jayfoad Nov 25, 2024
8c5a3a9
[mlir][docs] Update MLIR's PatternRewriter documentation (#116183)
jle-quel Nov 25, 2024
b5a11d3
[SelectOpt] Refactor to prepare for support more select-like operatio…
igogo-x86 Nov 25, 2024
4b71b37
[BOLT] DataAggregator support for binaries with multiple text segment…
paschalis-mpeis Nov 25, 2024
957c2ac
[BOLT] Fix for bughunter.sh in offline mode (#116649)
paschalis-mpeis Nov 25, 2024
b4d49fb
[libc] Remove RPC server API and use the header directly (#117075)
jhuber6 Nov 25, 2024
0ccc389
[libc] Make RPC header work with GCC9
jhuber6 Nov 25, 2024
52755ac
[flang][OpenMP] Use new modifier infrastructure for MAP/FROM/TO claus…
kparzysz Nov 25, 2024
506ca19
[OpenMP] Remove use of '__AMDGCN_WAVEFRONT_SIZE' (#113156)
jhuber6 Nov 25, 2024
4715dec
[XTensa] Use getSignedConstant() for negative values
nikic Nov 25, 2024
3699931
[M68k] Use getSignedConstant() where necessary
nikic Nov 25, 2024
18abc7e
[PatternMatch] Introduce m_c_Select (#114328)
davemgreen Nov 25, 2024
9b76e7f
Revert "[DAGCombiner] Add support for scalarising extracts of a vecto…
david-arm Nov 25, 2024
6f16a8b
[clang][bytecode] Use bitcasts to cast from integer to vector (#117547)
tbaederr Nov 25, 2024
2d62daa
[flang] AArch64 support for BIND(C) derived return types (#114051)
DavidTruby Nov 25, 2024
809c5ac
[X86] Modify tests for constrained rounding functions (#116951)
spavloff Nov 25, 2024
06cb5c9
[LLVM] Update ARM maintainers (#117002)
nikic Nov 25, 2024
4a7a27c
Revert "[SelectOpt] Refactor to prepare for support more select-like …
igogo-x86 Nov 25, 2024
a5506a3
[mlir][spirv] Use assemblyFormat to define {InBound}PtrAccessChainOp …
cydonialis Nov 25, 2024
6de97e9
[libc] Allow NVPTX targets to build in debug mode
jhuber6 Nov 25, 2024
387be04
[libc][NFC] Add const to RPC header members
jhuber6 Nov 25, 2024
7800d59
[SanitizerCoverage] Add gated tracing callbacks support to trace-cmp …
thetruestblue Nov 25, 2024
f9dca5b
[ADT] Add convenience function `filter_to_vector` (#117460)
kuhar Nov 25, 2024
7e3187e
Adding mlir prefix for missing places in TilingInterface.td (#117495)
ddubov100 Nov 25, 2024
57bbdbd
[SLP]Relax assertion in mask combine for non-power-of-2 number of ele…
alexey-bataev Nov 25, 2024
1b18ce5
[X86] vector-interleaved-load-i16-stride-2.ll - regenerate with AVX51…
RKSimon Nov 25, 2024
4d8eb00
[InstCombine] Remove SPF guard for trunc transforms (#117535)
nikic Nov 25, 2024
3de2147
[clang][codegen] Mention the invariant that LLVM demangler should be …
VitaNuo Nov 25, 2024
f953b5e
[SLP]Relax assertion about subvectors mask size
alexey-bataev Nov 25, 2024
b872c4c
[flang][Driver] Fix incorrect condition in test
tarunprabhu Nov 25, 2024
c9e606b
[mlir] Improve doc in `OpFormatGen.cpp` (NFC) (#117564)
chelini Nov 25, 2024
99fd1c5
[libc++][NFC] Don't add legacy transitive includes in <__chrono/durat…
philnik777 Nov 25, 2024
20bd029
[RISCV] Promote fldexp with Zfh. (#117396)
topperc Nov 25, 2024
3db4f5b
AMDGPU: Refine gfx950 xdl-write-vgpr hazard cases (#117285)
arsenm Nov 25, 2024
c3fe5ad
AMDGPU: Handle vcmpx+permalane gfx950 hazard (#117286)
arsenm Nov 25, 2024
27a8afa
AMDGPU: Handle gfx950 valu write vdst + permlane read hazard (#117287)
arsenm Nov 25, 2024
8a2311c
[Offload] Introduce offload-tblgen and initial new API implementation…
callumfare Nov 25, 2024
9cc2502
[clang] hexagon: fix link order for libc/builtins (#117057)
androm3da Nov 25, 2024
d88ed93
[NFC][RISCV] Refactor allocation of the stack space (#116625)
rzinsly Nov 25, 2024
e97fb22
AMDGPU: Add support for load transpose instructions for gfx950 (#117378)
arsenm Nov 25, 2024
6f8e7c1
AMDGPU: Add MC support for gfx950 V_BITOP3_B32/B16 (#117379)
arsenm Nov 25, 2024
8ea7800
[RISCV] Add test case for RVV CSRs with cm.push.
topperc Nov 23, 2024
7ad1084
AMDGPU: MC support for v_cvt_scale_[f16|f32]_fp8 of gfx950. (#117380)
arsenm Nov 25, 2024
91af15b
AMDGPU: MC support for v_cvt_scale_[f16|f32]_bf8 of gfx950. (#117381)
arsenm Nov 25, 2024
8997bf8
AMDGPU: MC support for v_cvt_scalef32_pk_{fp8|bf8}_f32 of gfx950. (#1…
arsenm Nov 25, 2024
70fef78
AMDGPU: MC support for v_cvt_scalef32_pk_f32_[fp|bf]8 of gfx950. (#11…
arsenm Nov 25, 2024
362d8fb
AMDGPU: MC support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 of gfx950.…
arsenm Nov 25, 2024
0077048
[C23] Fixed the value of BOOL_WIDTH (#117364)
AaronBallman Nov 25, 2024
0a140c4
[AMDGPU] Adds pre-commit test for fmul-select combine (#111107)
vg0204 Nov 25, 2024
29828b2
[RISCV] Fix double counting scalar CSRs with Zcmp when emitting cfi_o…
topperc Nov 25, 2024
d7c20a6
[libc][NFC] Move RPC opcodes to the 'shared/' directory as well
jhuber6 Nov 25, 2024
1a86d44
AMDGPU: MC support for v_cvt_scale_fp4<->f32 of gfx950. (#117417)
arsenm Nov 25, 2024
3cb2852
Reapply "[runtimes] Allow building against an installed LLVM tree"
arichardson Nov 25, 2024
d047bee
Revert "[Offload] Introduce offload-tblgen and initial new API implem…
jhuber6 Nov 25, 2024
a5dd646
Add extendhfxf2 into compiler rt (#113897)
biabbas Nov 25, 2024
ed6749a
[RISCV] Promote frexp with Zfh.
topperc Nov 25, 2024
b0bc467
[X86] Fix bad instregex in VPMOVSX/ZX znver4 512-bit patterns.
RKSimon Nov 25, 2024
bb88fd1
[DirectX] Calculate resource binding offsets using the lower bound (#…
bogner Nov 25, 2024
fdf1f69
[CGData][GMF] Skip No Params (#116548)
kyulee-com Nov 25, 2024
b0ca543
[memprof] Remove dead code in MemProfReader (NFC) (#117607)
kazutakahirata Nov 25, 2024
fe3c23b
Revert "[CGData][GMF] Skip No Params (#116548)"
kyulee-com Nov 25, 2024
c94d715
[RISCV] Add coverage for immediate sinking in switch vs branch cases
preames Nov 25, 2024
d733fa1
[RISCV] Consolidate VLS codepaths in stack frame manipulation [nfc] (…
preames Nov 25, 2024
5001f16
AMDGPU: MC support for v_cvt_scalef32_pk_{f|bf}16_fp4 of gfx950. (#11…
arsenm Nov 25, 2024
8e510b8
[RISCV] Fix a warning
kazutakahirata Nov 25, 2024
deab4e9
[flang][cuda][NFC] Add missing default values (#117610)
clementval Nov 25, 2024
96547de
[DirectX] Infrastructure to collect shader flags for each function (#…
bharadwajy Nov 25, 2024
466ff3e
[VPlan] Mark VPIRInstruction::getInstruction) as const (NFCI).
fhahn Nov 25, 2024
30af6fb
[VPlan] Group together helpers for retrieving various VPBlocks (NFCI).
fhahn Nov 25, 2024
9de73b2
[DWARF] Fix DWARTTypePrinter unable to print qualified name for DW_TA…
ZequanWu Nov 25, 2024
fe69a20
Reland [CGData][GMF] Skip No Params (#116548)
kyulee-com Nov 25, 2024
1df34f1
[MCA][X86] Add avx512 test coverage for VPMOV truncation instructions
RKSimon Nov 25, 2024
0988bf8
[LLVM-Reduce] - Null pointer handling during distinct metadata reduct…
rbintel Nov 25, 2024
935da49
AMDGPU: Pass HwMode to AMDGPUGenRegisterInfo (#117449)
arsenm Nov 25, 2024
ece4e12
[mlir][Affine] Split off delinearize parts that depend on last compon…
krzysz00 Nov 25, 2024
76f0ff8
[SLP]Add an extra check to avoid infinite vectorization attempts
alexey-bataev Nov 25, 2024
ab4e066
[X86][MC] Add R_X86_64_CODE_6_GOTTPOFF (#117277)
fzou1 Nov 25, 2024
4c91662
[libc] Resolve multi-line comment error (#117636)
Caslyn Nov 25, 2024
1973270
[libc] suppress string warning in case intrinsics are defined as macr…
SchrodingerZhu Nov 25, 2024
32432a6
[libc] suppress math library warnings on windows (#117638)
SchrodingerZhu Nov 25, 2024
1ea7ced
[mlir][py] Enable disabling loading all registered (#117643)
jpienaar Nov 25, 2024
97fe5fa
[Driver] Pass `--cuda-path` to test (#117415)
bzEq Nov 26, 2024
cac9783
[HLSL] Add `Increment`/`DecrementCounter` methods to structured buffe…
hekota Nov 26, 2024
c2bb056
[SelectionDAG][RISCV][AArch64] Allow f16 STRICT_FLDEXP to be promoted…
topperc Nov 26, 2024
2ab84a6
[X86][FP16][BF16] Improve vectorization of fcmp (#116153)
phoebewang Nov 26, 2024
c1a3960
[X86] Add APX imulzu support. (#116806)
daniel-zabawa Nov 26, 2024
2ed8c5d
[flang][OpenMP] Fix handling of nested loop wrappers in LowerWorkshar…
ivanradanov Nov 26, 2024
ebcaa57
[GISel] #undef macros when they are no longer needed. NFC (#117652)
topperc Nov 26, 2024
bf07a56
[LangRef] Remove extra commas of llvm.vp.ctlz (#117542)
LiqinWeng Nov 26, 2024
dd7aabf
[TTI][RISCV] Deduplicate type-based VP costing of vpcmp/vpcast (#117520)
LiqinWeng Nov 26, 2024
6633916
[RISCV] Remove getPostRAMutations (#117527)
wangpc-pp Nov 26, 2024
6657d4b
[TTI][RISCV] Unconditionally break critical edges to sink ADDI (#108889)
preames Nov 26, 2024
5dd48c4
AMDGPU: MC support for v_cvt_scalef32_pk32_f32_[fp|bf]6 of gfx950 (#1…
arsenm Nov 26, 2024
658db91
AMDGPU: MC support for v_cvt_scalef32_pk32_{bf|f}16_{bf|fp}6 of gfx95…
arsenm Nov 26, 2024
22503a9
AMDGPU: Support v_cvt_scalef32_pk32_{bf|f}6_{bf|fp}16 for gfx950 (#11…
arsenm Nov 26, 2024
c767570
AMDGPU: MC support for v_cvt_scalef32_pk_{bf|f}16_{bf|fp}8 of gfx950.…
arsenm Nov 26, 2024
d727b6f
AMDGPU: MC support for v_cvt_scalef32_pk_fp4_{f|bf}16 on gfx950. (#11…
arsenm Nov 26, 2024
c3377af
[RISCV][CostModel] add cost for cttz/ctlz under the non-zvbb (#117515)
LiqinWeng Nov 26, 2024
a87d484
AMDGPU: Support v_cvt_scalef32_2xpk16_{bf|fp}6_f32 for gfx950. (#117595)
arsenm Nov 26, 2024
5d650a6
AMDGPU: Add support for v_ashr_pk_i8/u8_i32 instructions for gfx950 (…
arsenm Nov 26, 2024
aa7eb57
AMDGPU: Add support for v_dot2_f32_bf16 instruction for gfx950 (#117597)
arsenm Nov 26, 2024
716364e
AMDGPU: Add support for v_dot2c_f32_bf16 instruction for gfx950 (#117…
arsenm Nov 26, 2024
7fc71f7
AMDGPU: Support buffer_atomic_pk_add_bf16 for gfx950 (#117599)
arsenm Nov 26, 2024
a5174de
AMDGPU: Add encodings for minimum3/maximum3 f32 for gfx950 (#117600)
arsenm Nov 26, 2024
ae719f0
AMDGPU: Add minimum3/maximum3 pkf16 for gfx950 encodings (#117601)
arsenm Nov 26, 2024
eb5cda4
[flang][cuda] cuf.allocate: Carry over stream to the runtime call (#1…
clementval Nov 26, 2024
ca184cf
[clangd] Support outgoing calls in call hierarchy (#77556)
HighCommander4 Nov 26, 2024
d77cab8
Revert "[clangd] Support outgoing calls in call hierarchy (#77556)" (…
HighCommander4 Nov 26, 2024
6e57186
[clang-format][NFC] Clean up RemoveBraces, RemoveSemi, etc.
owenca Nov 26, 2024
bc28260
[SelectionDAG] Require last operand of (STRICT_)FP_ROUND to be a Targ…
topperc Nov 26, 2024
90f5c8b
[LV][NFC] Auto-generate the test cases related to FindLastIV idioms. …
Mel-Chen Nov 26, 2024
5e3f615
[lldb/NativePDB] Don't create parentless blocks (#117581)
labath Nov 26, 2024
56eb559
[clang][FMV] Fix crash with cpu_specific attribute. (#115762)
labrinea Nov 26, 2024
8e924de
[AutoBump] Merge with 56eb559b (Nov 26)
jorickert Feb 20, 2025
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12 changes: 0 additions & 12 deletions .github/workflows/libcxx-build-and-test.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -33,18 +33,6 @@ concurrency:
group: ${{ github.workflow }}-${{ github.event.pull_request.number }}
cancel-in-progress: true


env:
# LLVM POST-BRANCH bump version
# LLVM POST-BRANCH add compiler test for ToT - 1, e.g. "Clang 17"
# LLVM RELEASE bump remove compiler ToT - 3, e.g. "Clang 15"
LLVM_HEAD_VERSION: "19" # Used compiler, update POST-BRANCH.
LLVM_PREVIOUS_VERSION: "18"
LLVM_OLDEST_VERSION: "17"
GCC_STABLE_VERSION: "13"
LLVM_SYMBOLIZER_PATH: "/usr/bin/llvm-symbolizer-19"
CLANG_CRASH_DIAGNOSTICS_DIR: "crash_diagnostics"

jobs:
stage1:
if: github.repository_owner == 'llvm'
Expand Down
8 changes: 8 additions & 0 deletions bolt/include/bolt/Profile/DataAggregator.h
Original file line number Diff line number Diff line change
Expand Up @@ -170,6 +170,9 @@ class DataAggregator : public DataReader {
std::string BuildIDBinaryName;

/// Memory map info for a single file as recorded in perf.data
/// When a binary has multiple text segments, the Size is computed as the
/// difference of the last address of these segments from the BaseAddress.
/// The base addresses of all text segments must be the same.
struct MMapInfo {
uint64_t BaseAddress{0}; /// Base address of the mapped binary.
uint64_t MMapAddress{0}; /// Address of the executable segment.
Expand Down Expand Up @@ -493,6 +496,11 @@ class DataAggregator : public DataReader {
/// and return a file name matching a given \p FileBuildID.
std::optional<StringRef> getFileNameForBuildID(StringRef FileBuildID);

/// Get a constant reference to the parsed binary mmap entries.
const std::unordered_map<uint64_t, MMapInfo> &getBinaryMMapInfo() {
return BinaryMMapInfo;
}

friend class YAMLProfileWriter;
};
} // namespace bolt
Expand Down
43 changes: 29 additions & 14 deletions bolt/lib/Profile/DataAggregator.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -95,6 +95,12 @@ cl::opt<bool> ReadPreAggregated(
"pa", cl::desc("skip perf and read data from a pre-aggregated file format"),
cl::cat(AggregatorCategory));

cl::opt<std::string>
ReadPerfEvents("perf-script-events",
cl::desc("skip perf event collection by supplying a "
"perf-script output in a textual format"),
cl::ReallyHidden, cl::init(""), cl::cat(AggregatorCategory));

static cl::opt<bool>
TimeAggregator("time-aggr",
cl::desc("time BOLT aggregator"),
Expand Down Expand Up @@ -167,8 +173,9 @@ void DataAggregator::findPerfExecutable() {
void DataAggregator::start() {
outs() << "PERF2BOLT: Starting data aggregation job for " << Filename << "\n";

// Don't launch perf for pre-aggregated files
if (opts::ReadPreAggregated)
// Don't launch perf for pre-aggregated files or when perf input is specified
// by the user.
if (opts::ReadPreAggregated || !opts::ReadPerfEvents.empty())
return;

findPerfExecutable();
Expand Down Expand Up @@ -464,6 +471,13 @@ void DataAggregator::filterBinaryMMapInfo() {

int DataAggregator::prepareToParse(StringRef Name, PerfProcessInfo &Process,
PerfProcessErrorCallbackTy Callback) {
if (!opts::ReadPerfEvents.empty()) {
outs() << "PERF2BOLT: using pre-processed perf events for '" << Name
<< "' (perf-script-events)\n";
ParsingBuf = opts::ReadPerfEvents;
return 0;
}

std::string Error;
outs() << "PERF2BOLT: waiting for perf " << Name
<< " collection to finish...\n";
Expand Down Expand Up @@ -2056,15 +2070,6 @@ std::error_code DataAggregator::parseMMapEvents() {
if (FileMMapInfo.first == "(deleted)")
continue;

// Consider only the first mapping of the file for any given PID
auto Range = GlobalMMapInfo.equal_range(FileMMapInfo.first);
bool PIDExists = llvm::any_of(make_range(Range), [&](const auto &MI) {
return MI.second.PID == FileMMapInfo.second.PID;
});

if (PIDExists)
continue;

GlobalMMapInfo.insert(FileMMapInfo);
}

Expand Down Expand Up @@ -2116,12 +2121,22 @@ std::error_code DataAggregator::parseMMapEvents() {
<< " using file offset 0x" << Twine::utohexstr(MMapInfo.Offset)
<< ". Ignoring profile data for this mapping\n";
continue;
} else {
MMapInfo.BaseAddress = *BaseAddress;
}
MMapInfo.BaseAddress = *BaseAddress;
}

BinaryMMapInfo.insert(std::make_pair(MMapInfo.PID, MMapInfo));
// Try to add MMapInfo to the map and update its size. Large binaries may
// span to multiple text segments, so the mapping is inserted only on the
// first occurrence.
if (!BinaryMMapInfo.insert(std::make_pair(MMapInfo.PID, MMapInfo)).second)
assert(MMapInfo.BaseAddress == BinaryMMapInfo[MMapInfo.PID].BaseAddress &&
"Base address on multiple segment mappings should match");

// Update mapping size.
const uint64_t EndAddress = MMapInfo.MMapAddress + MMapInfo.Size;
const uint64_t Size = EndAddress - BinaryMMapInfo[MMapInfo.PID].BaseAddress;
if (Size > BinaryMMapInfo[MMapInfo.PID].Size)
BinaryMMapInfo[MMapInfo.PID].Size = Size;
}

if (BinaryMMapInfo.empty()) {
Expand Down
3 changes: 3 additions & 0 deletions bolt/unittests/Core/CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,7 @@ set(LLVM_LINK_COMPONENTS
add_bolt_unittest(CoreTests
BinaryContext.cpp
MCPlusBuilder.cpp
MemoryMaps.cpp
DynoStats.cpp

DISABLE_LLVM_LINK_LLVM_DYLIB
Expand All @@ -17,6 +18,8 @@ target_link_libraries(CoreTests
PRIVATE
LLVMBOLTCore
LLVMBOLTRewrite
LLVMBOLTProfile
LLVMTestingSupport
)

foreach (tgt ${BOLT_TARGETS_TO_BUILD})
Expand Down
142 changes: 142 additions & 0 deletions bolt/unittests/Core/MemoryMaps.cpp
Original file line number Diff line number Diff line change
@@ -0,0 +1,142 @@
//===- bolt/unittest/Core/MemoryMaps.cpp ----------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

#include "bolt/Core/BinaryContext.h"
#include "bolt/Profile/DataAggregator.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/DebugInfo/DWARF/DWARFContext.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/TargetSelect.h"
#include "llvm/Testing/Support/Error.h"
#include "gtest/gtest.h"

using namespace llvm;
using namespace llvm::object;
using namespace llvm::ELF;
using namespace bolt;

namespace opts {
extern cl::opt<std::string> ReadPerfEvents;
} // namespace opts

namespace {

/// Perform checks on memory map events normally captured in perf. Tests use
/// the 'opts::ReadPerfEvents' flag to emulate these events, passing a custom
/// 'perf script' output to DataAggregator.
struct MemoryMapsTester : public testing::TestWithParam<Triple::ArchType> {
void SetUp() override {
initalizeLLVM();
prepareElf();
initializeBOLT();
}

protected:
void initalizeLLVM() {
llvm::InitializeAllTargetInfos();
llvm::InitializeAllTargetMCs();
llvm::InitializeAllAsmParsers();
llvm::InitializeAllDisassemblers();
llvm::InitializeAllTargets();
llvm::InitializeAllAsmPrinters();
}

void prepareElf() {
memcpy(ElfBuf, "\177ELF", 4);
ELF64LE::Ehdr *EHdr = reinterpret_cast<typename ELF64LE::Ehdr *>(ElfBuf);
EHdr->e_ident[llvm::ELF::EI_CLASS] = llvm::ELF::ELFCLASS64;
EHdr->e_ident[llvm::ELF::EI_DATA] = llvm::ELF::ELFDATA2LSB;
EHdr->e_machine = GetParam() == Triple::aarch64 ? EM_AARCH64 : EM_X86_64;
MemoryBufferRef Source(StringRef(ElfBuf, sizeof(ElfBuf)), "ELF");
ObjFile = cantFail(ObjectFile::createObjectFile(Source));
}

void initializeBOLT() {
Relocation::Arch = ObjFile->makeTriple().getArch();
BC = cantFail(BinaryContext::createBinaryContext(
ObjFile->makeTriple(), ObjFile->getFileName(), nullptr, true,
DWARFContext::create(*ObjFile.get()), {llvm::outs(), llvm::errs()}));
ASSERT_FALSE(!BC);
}

char ElfBuf[sizeof(typename ELF64LE::Ehdr)] = {};
std::unique_ptr<ObjectFile> ObjFile;
std::unique_ptr<BinaryContext> BC;
};
} // namespace

#ifdef X86_AVAILABLE

INSTANTIATE_TEST_SUITE_P(X86, MemoryMapsTester,
::testing::Values(Triple::x86_64));

#endif

#ifdef AARCH64_AVAILABLE

INSTANTIATE_TEST_SUITE_P(AArch64, MemoryMapsTester,
::testing::Values(Triple::aarch64));

#endif

/// Check that the correct mmap size is computed when we have multiple text
/// segment mappings.
TEST_P(MemoryMapsTester, ParseMultipleSegments) {
const int Pid = 1234;
StringRef Filename = "BINARY";
opts::ReadPerfEvents = formatv(
"name 0 [000] 0.000000: PERF_RECORD_MMAP2 {0}/{0}: "
"[0xabc0000000(0x1000000) @ 0x11c0000 103:01 1573523 0]: r-xp {1}\n"
"name 0 [000] 0.000000: PERF_RECORD_MMAP2 {0}/{0}: "
"[0xabc2000000(0x8000000) @ 0x31d0000 103:01 1573523 0]: r-xp {1}\n",
Pid, Filename);

BC->SegmentMapInfo[0x11da000] =
SegmentInfo{0x11da000, 0x10da000, 0x11ca000, 0x10da000, 0x10000, true};
BC->SegmentMapInfo[0x31d0000] =
SegmentInfo{0x31d0000, 0x51ac82c, 0x31d0000, 0x3000000, 0x200000, true};

DataAggregator DA("");
BC->setFilename(Filename);
Error Err = DA.preprocessProfile(*BC);

// Ignore errors from perf2bolt when parsing memory events later on.
ASSERT_THAT_ERROR(std::move(Err), Succeeded());

auto &BinaryMMapInfo = DA.getBinaryMMapInfo();
auto El = BinaryMMapInfo.find(Pid);
// Check that memory mapping is present and has the expected size.
ASSERT_NE(El, BinaryMMapInfo.end());
ASSERT_EQ(El->second.Size, static_cast<uint64_t>(0xb1d0000));
}

/// Check that DataAggregator aborts when pre-processing an input binary
/// with multiple text segments that have different base addresses.
TEST_P(MemoryMapsTester, MultipleSegmentsMismatchedBaseAddress) {
const int Pid = 1234;
StringRef Filename = "BINARY";
opts::ReadPerfEvents = formatv(
"name 0 [000] 0.000000: PERF_RECORD_MMAP2 {0}/{0}: "
"[0xabc0000000(0x1000000) @ 0x11c0000 103:01 1573523 0]: r-xp {1}\n"
"name 0 [000] 0.000000: PERF_RECORD_MMAP2 {0}/{0}: "
"[0xabc2000000(0x8000000) @ 0x31d0000 103:01 1573523 0]: r-xp {1}\n",
Pid, Filename);

BC->SegmentMapInfo[0x11da000] =
SegmentInfo{0x11da000, 0x10da000, 0x11ca000, 0x10da000, 0x10000, true};
// Using '0x31d0fff' FileOffset which triggers a different base address
// for this second text segment.
BC->SegmentMapInfo[0x31d0000] =
SegmentInfo{0x31d0000, 0x51ac82c, 0x31d0fff, 0x3000000, 0x200000, true};

DataAggregator DA("");
BC->setFilename(Filename);
ASSERT_DEATH(
{ Error Err = DA.preprocessProfile(*BC); },
"Base address on multiple segment mappings should match");
}
4 changes: 2 additions & 2 deletions bolt/utils/bughunter.sh
Original file line number Diff line number Diff line change
Expand Up @@ -131,7 +131,7 @@ if [[ $FAIL -eq "0" ]]; then
fi
else
echo "Did it pass? Type the return code [0 = pass, 1 = fail]"
read -n1 PASS
read -n1 FAIL
fi
if [[ $FAIL -eq "0" ]] ; then
echo " Warning: optimized binary passes."
Expand Down Expand Up @@ -205,7 +205,7 @@ while [[ "$CONTINUE" -ne "0" ]] ; do
echo " OPTIMIZED_BINARY failure=$FAIL"
else
echo "Did it pass? Type the return code [0 = pass, 1 = fail]"
read -n1 PASS
read -n1 FAIL
fi
else
FAIL=1
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -303,7 +303,7 @@ void InfiniteLoopCheck::check(const MatchFinder::MatchResult &Result) {
}
}

if (ExprMutationAnalyzer::isUnevaluated(LoopStmt, *LoopStmt, *Result.Context))
if (ExprMutationAnalyzer::isUnevaluated(LoopStmt, *Result.Context))
return;

if (isAtLeastOneCondVarChanged(Func, LoopStmt, Cond, Result.Context))
Expand Down
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