read_liberty: support loopy retention cells

[widlarizer]

Fixes #5491. Retention cells seem to be advanced PDK cells that allow retention of flop state, usually while the main power domain is off. Balloon retention cells loop the output of a DFFSR through a latch to its input. For this reason, to construct them correctly in read_liberty, we have to create latch and ff group state wires before we build the logic that models them.

Additionally, to test this change, this PR modifies filterlib -verilogsim to avoid emitting unsynthesizable verilog when possible. This is possible whenever both clear_preset_var* are defined as either low or high by emitting a process for either state variable separately and adjusting the precedence of clear and preset.

This allowed me to cover the new functionality with tests/liberty/read_liberty.ys which proves equivalence between the cell model for retention.lib created by read_liberty and by filterlib -verilogsim.