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Pipelined_RISC-V_Processor

CSCE 3301 – Computer Architecture

Fall 2020

This is a pipelined RISC-V datapath implementation supporting all RV32I (40 instructions).

Basic testcase is provided. The testcase is loaded in the instruction memory, and is provided as an assembly text and binary text as well.

This implementation uses single memory for instructions and data.

Datapath

Pipelined_Final

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