Merge pull request #29 from ladyada/master

add support for second SPI - tested!
adafruit · Aug 22, 2018 · 96a325a · 96a325a
2 parents b0a7115 + 73cacdb
commit 96a325a
Show file tree

Hide file tree

Showing 2 changed files with 9 additions and 5 deletions.
diff --git a/src/adafruit_blinka/board/raspi_23.py b/src/adafruit_blinka/board/raspi_23.py
@@ -33,8 +33,12 @@
 D17 = pin.D17
 D18 = pin.D18
 D19 = pin.D19
+MISO_1 = pin.D19
 D20 = pin.D20
+MOSI_1 = pin.D20
 D21 = pin.D21
+SCLK_1 = pin.D21
+SCK_1 = pin.D21
 D22 = pin.D22
 D23 = pin.D23
 D24 = pin.D24

diff --git a/src/adafruit_blinka/microcontroller/raspi_23/pin.py b/src/adafruit_blinka/microcontroller/raspi_23/pin.py
@@ -91,12 +91,12 @@ def value(self, val=None):
 D17 = Pin(17)
 D18 = Pin(18)
 D19 = Pin(19)
-MISO_2 = Pin(19)
+MISO_1 = Pin(19)
 D20 = Pin(20)
-MOSI_2 = Pin(20)
+MOSI_1 = Pin(20)
 D21 = Pin(21)
-SCLK_2 = Pin(21)
-SCK_2 = Pin(21)
+SCLK_1 = Pin(21)
+SCK_1 = Pin(21)
 D22 = Pin(22)
 D23 = Pin(23)
 D24 = Pin(24)
@@ -105,7 +105,7 @@ def value(self, val=None):
 D27 = Pin(27)
 
 # ordered as spiId, sckId, mosiId, misoId
-spiPorts = ((0, SCLK, MOSI, MISO), (1, SCLK_2, MOSI_2, MISO_2))
+spiPorts = ((0, SCLK, MOSI, MISO), (1, SCLK_1, MOSI_1, MISO_1))
 
 # ordered as uartId, txId, rxId
 uartPorts = (