Add Feature - BSX Loading

dist/Cores/agg23.SNES/data.json

@@ -2,13 +2,21 @@
   "data": {
     "magic": "APF_VER_1",
     "data_slots": [
-      {
+	  {
         "name": "Cartridge",
         "id": 0,
         "required": true,
         "parameters": "0x109",
         "extensions": ["smc", "sfc", "bs"],
         "address": "0x10000000"
+      },
+	  {
+        "name": "Bios",
+        "id": 1,
+        "required": true,
+        "filename": "bios.rom",
+        "extensions": ["rom"],
+        "address": "0x10000000"
       },
       {
         "name": "Save",

dist/Cores/agg23.SNES/interact.json

@@ -31,6 +31,17 @@
         "writeonly": true,
         "defaultval": 0,
         "value": 1
+      },
+	  {
+        "name": "SuperFX Fastrom",
+        "id": 17,
+        "type": "check",
+        "enabled": true,
+        "address": "0x88",
+        "persist": true,
+        "writeonly": true,
+        "defaultval": 1,
+        "value": 1
       },
       {
         "name": "Use Multitap",

src/fpga/ap_core.qsf

@@ -748,6 +748,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE core/rtl/mister_top/sync_fifo.sv
 set_global_assignment -name MIF_FILE core/rtl/chip/DSP/dsp11b23410_p.mif
 set_global_assignment -name MIF_FILE core/rtl/chip/DSP/dsp11b23410_d.mif
 set_global_assignment -name MIF_FILE core/rtl/chip/CX4/drom.mif
+set_global_assignment -name MIF_FILE core/rtl/chip/BSX/bsx121-124.mif
 set_global_assignment -name SYSTEMVERILOG_FILE core/rtl/mister_top/sound_i2s.sv
 set_global_assignment -name SYSTEMVERILOG_FILE core/rtl/mister_top/rom_parser.sv
 set_global_assignment -name SYSTEMVERILOG_FILE core/rtl/mister_top/data_unloader.sv
@@ -792,4 +793,4 @@ set_global_assignment -name QIP_FILE core/mf_pllbase_pal.qip
 set_global_assignment -name SIP_FILE core/mf_pllbase_pal.sip
 set_parameter -name PAL_PLL '0 -entity core_top
 set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

src/fpga/core/core_top.sv

@@ -358,6 +358,9 @@ module core_top (
         end
         32'h84: begin
           gsu_turbo_enabled <= bridge_wr_data[0];
+        end
+	    32'h88: begin
+          gsu_fastrom_enabled <= bridge_wr_data[0];
         end
         32'h100: begin
           multitap_enabled <= bridge_wr_data[0];
@@ -679,6 +682,7 @@ module core_top (
 
   reg cpu_turbo_enabled = 0;
   reg gsu_turbo_enabled = 0;
+  reg gsu_fastrom_enabled = 1;
 
   reg multitap_enabled = 0;
   reg lightgun_enabled = 0;
@@ -695,6 +699,7 @@ module core_top (
 
   wire cpu_turbo_enabled_s;
   wire gsu_turbo_enabled_s;
+  wire gsu_fastrom_enabled_s;
 
   wire multitap_enabled_s;
   wire lightgun_enabled_s;
@@ -707,12 +712,13 @@ module core_top (
   wire blend_enabled_s;
 
   synch_3 #(
-      .WIDTH(25)
+      .WIDTH(26)
   ) settings_s (
       {
         reset_button,
         cpu_turbo_enabled,
         gsu_turbo_enabled,
+	    gsu_fastrom_enabled,
         multitap_enabled,
         lightgun_enabled,
         lightgun_type,
@@ -726,6 +732,7 @@ module core_top (
         reset_button_s,
         cpu_turbo_enabled_s,
         gsu_turbo_enabled_s,
+	    gsu_fastrom_enabled_s,
         multitap_enabled_s,
         lightgun_enabled_s,
         lightgun_type_s,
@@ -771,6 +778,7 @@ module core_top (
       // Settings
       .cpu_turbo_enabled(cpu_turbo_enabled_s),
       .gsu_turbo_enabled(gsu_turbo_enabled_s),
+      .gsu_fastrom_enabled(gsu_fastrom_enabled_s),
 
       .multitap_enabled(multitap_enabled_s),
       .lightgun_enabled(lightgun_enabled_s),

src/fpga/core/rtl/chip/BSX/bsx121-124.mif

@@ -1,3 +1,6 @@
+// This file contains the config data for the bsx bios which you can edit with tools like sat wave - https://github.com/LuigiBlood/sat_wave/releases 
+//The file has been changed to read " Welcome to Analogue Pocket satellaview support! from 000 - 03A
+
 
 WIDTH=8;
 DEPTH=550;
@@ -28,20 +31,20 @@ CONTENT BEGIN
 	013  :   74;
 	014  :   6F;
 	015  :   20;
-	016  :   4D;
-	017  :   69;
-	018  :   53;
-	019  :   54;
-	01A  :   65;
-	01B  :   72;
-	01C  :   21;
+	016  :   41;
+	017  :   6E;
+	018  :   6C;
+	019  :   6F;
+	01A  :   67;
+	01B  :   75;
+	01C  :   65;
 	01D  :   20;
-	01E  :   20;
-	01F  :   20;
-	020  :   20;
-	021  :   20;
-	022  :   20;
-	023  :   20;
+	01E  :   50;
+	01F  :   6F;
+	020  :   63;
+	021  :   6B;
+	022  :   65;
+	023  :   74;
 	024  :   0D;
 	025  :   20;
 	026  :   53;
@@ -65,13 +68,13 @@ CONTENT BEGIN
 	038  :   74;
 	039  :   21;
 	03A  :   00;
-	03B  :   00;
-	03C  :   00;
-	03D  :   00;
-	03E  :   00;
-	03F  :   00;
-	040  :   00;
-	041  :   00;
+	03B  :   20;
+	03C  :   45;
+	03D  :   6E;
+	03E  :   6A;
+	03F  :   6F;
+	040  :   79;
+	041  :   21;
 	042  :   00;
 	043  :   00;
 	044  :   00;

src/fpga/core/rtl/chip/GSU/GSU.vhd

@@ -7,33 +7,34 @@ use work.GSU_PKG.all;
 
 entity GSU is
 	port(
-		CLK			: in std_logic;
+		CLK		: in std_logic;
 
-		RST_N			: in std_logic;
+		RST_N		: in std_logic;
 		ENABLE		: in std_logic;
 
 		ADDR   		: in std_logic_vector(23 downto 0);
-		DI				: in std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		RD_N			: in std_logic;
-		WR_N			: in std_logic;
+		DI		: in std_logic_vector(7 downto 0);
+		DO		: out std_logic_vector(7 downto 0);
+		RD_N		: in std_logic;
+		WR_N		: in std_logic;
 
 		SYSCLKF_CE	: in std_logic;
 		SYSCLKR_CE	: in std_logic;
 
-		TURBO			: in std_logic;
+		TURBO		: in std_logic;
+		FASTROM		: in std_logic;
 
-		IRQ_N			: out std_logic;
+		IRQ_N		: out std_logic;
 
-		ROM_A   		: out std_logic_vector(20 downto 0);
+		ROM_A   	: out std_logic_vector(20 downto 0);
 		ROM_DI		: in std_logic_vector(7 downto 0);
-		ROM_RD_N		: out std_logic;							--for MISTer sdram
+		ROM_RD_N	: out std_logic;							--for MISTer sdram
 
-		RAM_A			: out std_logic_vector(16 downto 0);
+		RAM_A		: out std_logic_vector(16 downto 0);
 		RAM_DI		: in std_logic_vector(7 downto 0);
 		RAM_DO		: out std_logic_vector(7 downto 0);
-		RAM_WE_N		: out std_logic;
-		RAM_CE_N		: out std_logic;
+		RAM_WE_N	: out std_logic;
+		RAM_CE_N	: out std_logic;
 
 		DBG_IN_CACHE: out std_logic;
 		DBG_MC		: out Microcode_r;
@@ -392,7 +393,7 @@ begin
 
 
 	--CPU Core
-	CODE_IN_ROM <= '1' when PBR <= x"5F" else '0';
+	CODE_IN_ROM <= '1' when PBR <= x"5F" or (PBR >= x"80" and FASTROM = '1') else '0';
 	CODE_IN_RAM <= '1' when PBR(7 downto 1) = "0111000" else '0';
 	IN_CACHE <= '1' when CACHE_POS(15 downto 9) = "0000000" else '0';
 	VAL_CACHE <= CACHE_VALID(to_integer(CACHE_POS(8 downto 4)));

src/fpga/core/rtl/chip/GSU/GSUMap.vhd

@@ -8,34 +8,34 @@ use IEEE.STD_LOGIC_TEXTIO.all;
 
 entity GSUMap is
 	port(
-		MCLK			: in std_logic;
-		RST_N			: in std_logic;
+		MCLK		: in std_logic;
+		RST_N		: in std_logic;
 		ENABLE		: in std_logic := '1';
 
-		CA   			: in std_logic_vector(23 downto 0);
-		DI				: in std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
+		CA   		: in std_logic_vector(23 downto 0);
+		DI		: in std_logic_vector(7 downto 0);
+		DO		: out std_logic_vector(7 downto 0);
 		CPURD_N		: in std_logic;
 		CPUWR_N		: in std_logic;
 
-		PA				: in std_logic_vector(7 downto 0);
+		PA		: in std_logic_vector(7 downto 0);
 		PARD_N		: in std_logic;
 		PAWR_N		: in std_logic;
 
-		ROMSEL_N		: in std_logic;
-		RAMSEL_N		: in std_logic;
+		ROMSEL_N	: in std_logic;
+		RAMSEL_N	: in std_logic;
 
 		SYSCLKF_CE	: in std_logic;
 		SYSCLKR_CE	: in std_logic;
 		REFRESH		: in std_logic;
 
-		IRQ_N			: out std_logic;
+		IRQ_N		: out std_logic;
 
-		ROM_ADDR		: out std_logic_vector(22 downto 0);
-		ROM_Q			: in  std_logic_vector(15 downto 0);
-		ROM_CE_N		: out std_logic;
-		ROM_OE_N		: out std_logic;
-		ROM_WORD		: out std_logic;
+		ROM_ADDR	: out std_logic_vector(22 downto 0);
+		ROM_Q		: in  std_logic_vector(15 downto 0);
+		ROM_CE_N	: out std_logic;
+		ROM_OE_N	: out std_logic;
+		ROM_WORD	: out std_logic;
 
 		BSRAM_ADDR	: out std_logic_vector(19 downto 0);
 		BSRAM_D		: out std_logic_vector(7 downto 0);
@@ -44,12 +44,13 @@ entity GSUMap is
 		BSRAM_OE_N	: out std_logic;
 		BSRAM_WE_N	: out std_logic;
 
-		MAP_ACTIVE  : out std_logic;
-		MAP_CTRL		: in std_logic_vector(7 downto 0);
-		ROM_MASK		: in std_logic_vector(23 downto 0);
+		MAP_ACTIVE      : out std_logic;
+		MAP_CTRL	: in std_logic_vector(7 downto 0);
+		ROM_MASK	: in std_logic_vector(23 downto 0);
 		BSRAM_MASK	: in std_logic_vector(23 downto 0);
 
-		TURBO		   : in std_logic
+		TURBO		: in std_logic;
+		FASTROM   	: in std_logic
 	);
 end GSUMap;
 
@@ -67,32 +68,33 @@ begin
 
 	GSU : entity work.GSU
 	port map(
-		CLK			=> MCLK,
-		RST_N			=> RST_N and MAP_SEL,
+		CLK		=> MCLK,
+		RST_N		=> RST_N and MAP_SEL,
 		ENABLE		=> ENABLE,
 
-		ADDR			=> CA,
-		DO				=> DO,
-		DI				=> DI,
-		RD_N			=> CPURD_N,
-		WR_N			=> CPUWR_N,
+		ADDR		=> CA,
+		DO		=> DO,
+		DI		=> DI,
+		RD_N		=> CPURD_N,
+		WR_N		=> CPUWR_N,
 
 		SYSCLKF_CE	=> SYSCLKF_CE,
 		SYSCLKR_CE	=> SYSCLKR_CE,
 
-		IRQ_N			=> IRQ_N,
+		IRQ_N		=> IRQ_N,
 
-		ROM_A			=> ROM_A,
+		ROM_A		=> ROM_A,
 		ROM_DI		=> ROM_Q(7 downto 0),
-		ROM_RD_N		=> ROM_OE_N,
+		ROM_RD_N	=> ROM_OE_N,
 
-		RAM_A			=> RAM_A,
+		RAM_A		=> RAM_A,
 		RAM_DI		=> BSRAM_Q,
 		RAM_DO		=> BSRAM_D,
-		RAM_WE_N		=> RAM_WE_N,
-		RAM_CE_N		=> BSRAM_CE_N,
+		RAM_WE_N	=> RAM_WE_N,
+		RAM_CE_N	=> BSRAM_CE_N,
 
-		TURBO			=> TURBO
+		TURBO		=> TURBO,
+		FASTROM		=> FASTROM
 	);
 
 	ROM_ADDR 	<= ("00" & ROM_A) and ROM_MASK(22 downto 0);
@@ -103,4 +105,4 @@ begin
 	BSRAM_OE_N 	<= not RAM_WE_N;
 	BSRAM_WE_N 	<= RAM_WE_N;
 
-end rtl;
+end rtl;

src/fpga/core/rtl/main.v

@@ -58,6 +58,7 @@ module main #(
 
     output GSU_ACTIVE,
     input  GSU_TURBO,
+    input  GSU_FASTROM,
 
     input        BLEND,
     input        PAL,
@@ -527,7 +528,8 @@ module main #(
           .rom_mask  (ROM_MASK),
           .bsram_mask(RAM_MASK),
 
-          .turbo(GSU_TURBO)
+          .turbo(GSU_TURBO),
+	      .fastrom(GSU_FASTROM)
       );
     end else assign MAP_ACTIVE[2] = 0;
   endgenerate

src/fpga/core/rtl/mister_top/SNES.sv

@@ -9,6 +9,7 @@ module MAIN_SNES (
     // Settings
     input wire cpu_turbo_enabled,
     input wire gsu_turbo_enabled,
+    input wire gsu_fastrom_enabled,
 
     input wire multitap_enabled,
     input wire lightgun_enabled,
@@ -330,6 +331,7 @@ module MAIN_SNES (
 
       // .GSU_ACTIVE(GSU_ACTIVE),
       .GSU_TURBO(gsu_turbo_enabled),
+      .GSU_FASTROM(gsu_fastrom_enabled),
 
       .ROM_TYPE(rom_type),
       .ROM_MASK(rom_mask),