write_addr_reg unused debug

[jiandongg]

Debug the dangerous use of write_addr, should use write_addr_reg in your original code design. This bug could cause unexpected write/erase action if write_addr is not stable in the next clk of write_enable.
Your testbench may need to be modified, too. But I can't run your testbench on my computer. :D
Testbench modification may like this:
# write some data
write_addr.next = 0
write_data.next = 0x0123456789ABCDEF
write_delete.next = 0
write_enable.next = 1
yield clk.posedge
write_enable.next = 0
yield clk.posedge
to
# write some data
write_addr.next = 0
write_data.next = 0x0123456789ABCDEF
write_delete.next = 0
write_enable.next = 1
yield clk.posedge
write_addr.next = 0
write_data.next = 0
write_delete.next = 0
write_enable.next = 0
yield clk.posedge
THANKS FOR YOUR PROJECT A LOT!