docs: add project daq2

[adiceline]

PR Description

Added documentation for the project DAQ2

PR Type

• Bug fix (change that fixes an issue)
• New feature (change that adds new functionality)
• Breaking change (has dependencies in other repos or will cause CI to fail)
• Documentation

PR Checklist

• I have followed the code style guidelines
• I have performed a self-review of changes
• I have compiled all hdl projects and libraries affected by this PR
• I have tested in hardware affected projects, at least on relevant boards
• I have commented my code, at least hard-to-understand parts
• I have signed off all commits from this PR
• I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
• I have not introduced new Warnings/Critical Warnings on compilation
• I have added new hdl testbenches or updated existing ones

[CLAassistant]

All committers have signed the CLA.

[IuliaCMoldovan]

The link operates in subclass 1 (see for zynq 7 series, zynq ultrascale and microblaze).
This should be updated in the block diagram as well

[IuliaCMoldovan]

• - Should write on the signals exiting the util_adxcvr, that they are rx_out_clk_0 and tx_out_clk_0 respectively
• - The subclass should be corrected
• - The link parameters should be written (like here)
• - The bus width for the RX DMA should be 128 (source) and 64 (destination)
• - Should write that the rx/tx_divclk is in fact the rx/tx global clock, and that it is rx/tx lane rate / 40 = ...
• - The carriers should be in alphabetical order
• - In the top left corner, where there is only "Zynq", should write "7 series/UltraScale". I will specify this in the template later on (now we don't write it like this yet)
• - There is no trx_ref_clk_p/n signal, but there are 2 separate signals in the block design (tx_ref_clk_0 which goes to QPLL and rx_ref_clk_0 which goes to the CPLLs)
• - There are SYSREF signals which are not added in the diagram (they go to the RX/TX JESD LINK module)

[IuliaCMoldovan]

Suggested change

	Evaluation board block diagram
	^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
	The data path and clock domains in the evaluation board are depicted in the below diagram:
	.. image:: daq2_board_block_diagram.svg
	:width: 800
	:align: center
	:alt: DAQ2 evaluation board block diagram

Something of the sort, not necessarily 1:1 like this.
And to add this block diagram https://wiki.analog.com/resources/fpga/peripherals/jesd204/tutorial/hdl_xilinx#ad-fmcdaq2-ebz_block_diagram

[IuliaCMoldovan]

The dtsi should be removed, and only the dts-es should be added:

• https://github.com/analogdevicesinc/linux/blob/main/arch/microblaze/boot/dts/kc705_fmcdaq2.dts
• https://github.com/analogdevicesinc/linux/blob/main/arch/microblaze/boot/dts/vc707_fmcdaq2.dts
• https://github.com/analogdevicesinc/linux/blob/main/arch/microblaze/boot/dts/kcu105_fmcdaq2.dts
• https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zc706-adv7511-fmcdaq2.dts
• https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-fmcdaq2.dts
• https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-fmcdaq2_m4_l4.dts