library/spi_engine: SDO Extension upgrade #1808
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Overall this seems headed in a nice direction, and thanks for also doing a lot of small fixes and improvements to the existing code along the way.
About the version: is this going to be a minor version or a major version bump? I understand that the removed register was not used anywhere (it was broken even), but technically we're breaking anything that relied on it. Also changing the behavior of the SDI & SDO FIFOs.
Also, please check timing on ad4052/de10nano just to be sure if it's all good.
| @@ -69,7 +70,7 @@ module spi_engine_execution #( | |||
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| input echo_sclk, | |||
| output reg sclk, | |||
| output reg sdo, | |||
| output reg [NUM_OF_SDI-1:0] sdo, | |||
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Since now this applies to both sdi and sdo, please rename it to reflect the change.
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Similar to my other comment, does it make sense to always have NUM_OF_SDI and NUM_OF_SDO the same? There are chips that have multiple SDO lines (so multiple SPI on the SPI Engine) but only one SDI line (so only one SDO line on the SPI Engine).
library/spi_engine/spi_engine_execution/spi_engine_execution_shiftreg.v
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library/spi_engine/spi_engine_execution/spi_engine_execution_shiftreg_data_assemble.v
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* Extend SDO support to 8 (symmetrical with SDI support); * Update SDI to use asymmetrical FIFO; * Insert symmetrical FIFO for the SDO; * Insert SPI lane mask configuration instruction to reg 2'b11; * Insert offload active interface for interconnect and execution; * Remove register 8'h3b from spi engine regmap. Prefetching on offload work iff all lanes are active. Signed-off-by: Carlos Souza <[email protected]>
* Update documentation to include the changes done for supporting more than one SDO lane. * Update the register map. Signed-off-by: Carlos Souza <[email protected]>
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| for ``NUM_OF_SDI`` lanes it is necessary to read ``NUM_OF_SDI`` times. Reading | ||
| always starts from lane 0. |
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Does this actually depend on NUM_OF_SDI or does it depend on how many lanes are enabled in SPI Lane Mask Register? It sounds like this is how SDO is working, so I would expect SDI to be the same but they way that it is currently worded makes it sound different.
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| .. _spi_engine spi-lane-mask-register: | ||
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| SPI Lane Mask Register |
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What is the plan to handle chips with a single SDO and multiple SDI lines? It seems like to be able to make those work in full-duplex, we would need a separate mask for each.
| @@ -69,7 +70,7 @@ module spi_engine_execution #( | |||
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| input echo_sclk, | |||
| output reg sclk, | |||
| output reg sdo, | |||
| output reg [NUM_OF_SDI-1:0] sdo, | |||
There was a problem hiding this comment.
Similar to my other comment, does it make sense to always have NUM_OF_SDI and NUM_OF_SDO the same? There are chips that have multiple SDO lines (so multiple SPI on the SPI Engine) but only one SDI line (so only one SDO line on the SPI Engine).
PR Description
Upgrade SPI engine to support up to 8 lanes. For that, a new register was inserted into Configuration Write Instruction, which is responsible for setting the lane mask. Each bit represents a lane.
This PR also removes register 8'h3b from the SPI Engine regmap.
PR Type
PR Checklist