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corundum_netstack: Add support for 10 GbE implementation (for K26-based AD-GMSL2ETH-SL board) #1832

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corundum_netstack: Add support for 10 GbE implementation (for K26-based AD-GMSL2ETH-SL board) #1832

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a302db5
corundum/ethernet: Add support for K26-based board
alin724 Jul 14, 2025
a668e96
corundum/interfaces: Add SFP-related interface
alin724 Jul 14, 2025
acfbf9d
corundum/scripts: Add K26 support
alin724 Jul 14, 2025
f37468c
ad_gmsl2eth_sl: Update the support to the latest Corundum NetStack ve…
alin724 Jul 14, 2025
911503f
docs/library/corundum: Add K26 support
alin724 Jul 14, 2025
34be9a9
docs/ad_gmsl2eth_sl: Update to latest Corundum NetStack version
alin724 Jul 14, 2025
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6 changes: 4 additions & 2 deletions docs/library/corundum/ethernet/index.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,8 @@ Corundum Ethernet Core

VCU118 <vcu118/index>

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Remove extra line.

K26 <k26/index>

The :git-hdl:`Corundum Ethernet Core <library/corundum/ethernet_core>` is used
by the Corundum Network Stack. The Ethernet Core is specific to each FPGA board
and encompasses the Ethernet physical layer and other auxiliary structures such
Expand All @@ -19,12 +21,12 @@ Depending on the board for which the IP is built, different HDL component
diagrams will be available.

* :ref:`corundum_ethernet_core_vcu118`
* :ref:`corundum_ethernet_core_k26`

Features
--------------------------------------------------------------------------------

* Supports 100G Ethernet-based systems that uses the CMAC core on the VCU118
board
* Supports 10/100 GbE implementations as follows: 100 GbE by leveraging on the Xilinx's CMAC IP core (on the VCU118 evaluation kit) and 10 GbE by using the Corundum's support (on the K26-based AD-GMSL2ETH-SL evaluation kit).
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Split into multiple lines.


Files
--------------------------------------------------------------------------------
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34 changes: 34 additions & 0 deletions docs/library/corundum/ethernet/k26/index.rst
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Original file line number Diff line number Diff line change
@@ -0,0 +1,34 @@
.. _corundum_ethernet_core_k26:

Corundum Ethernet Core for K26
================================================================================

.. hdl-component-diagram::

Files
--------------------------------------------------------------------------------

.. list-table::
:header-rows: 1

* - Name
- Description
* - :git-hdl:`library/corundum/ethernet_core/ethernet_core_k26.v`
- Verilog source for the Ethernet Core top module for the K26-based AD-GMSL2ETH-SL evaluation kit.
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Split into multiple lines.

* - :git-hdl:`library/corundum/ethernet_core/ethernet_ip.tcl`
- TCL script to generate the Vivado IP-integrator project.

Configuration Parameters
--------------------------------------------------------------------------------

.. hdl-parameters::

Interface
--------------------------------------------------------------------------------

.. hdl-interfaces::

References
--------------------------------------------------------------------------------

* HDL IP core at :git-hdl:`library/corundum/ethernet_core`
2 changes: 1 addition & 1 deletion docs/library/corundum/ethernet/vcu118/index.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@ Files
- Description
* - :git-hdl:`library/corundum/ethernet_core/ethernet_core_vcu118.v`
- Verilog source for the Ethernet Core top module for the VCU118 board.
* - :git-hdl:`library/corundum/ethernet_core/eternet_ip.tcl`
* - :git-hdl:`library/corundum/ethernet_core/ethernet_ip.tcl`
- TCL script to generate the Vivado IP-integrator project.

Configuration Parameters
Expand Down
45 changes: 21 additions & 24 deletions docs/projects/ad_gmsl2eth_sl/index.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -71,24 +71,23 @@ CPU/Memory interconnects addresses
The addresses are dependent on the architecture of the FPGA, having an offset
added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`).

======================== ===========
Instance Address
======================== ===========
mipi_csi2_rx_subsyst_0 0x84A0_0000
mipi_csi2_rx_subsyst_1 0x84A2_0000
axi_iic_mipi 0x84A4_0000
v_frmbuf_wr_0 0x84A6_0000
v_frmbuf_wr_1 0x84A8_0000
v_frmbuf_wr_2 0x84AA_0000
v_frmbuf_wr_3 0x84AC_0000
v_frmbuf_wr_4 0x84AE_0000
v_frmbuf_wr_5 0x84B0_0000
v_frmbuf_wr_6 0x84B2_0000
v_frmbuf_wr_7 0x84B4_0000
axi_pwm_gen_0 0x84B6_0000
corundum/s_axil_ctrl 0xA000_0000
corundum/s_axil_app_ctrl 0xA800_0000
======================== ===========
============================================ ===========
Instance Address
============================================ ===========
mipi_csi2_rx_subsyst_0 0x84A0_0000
mipi_csi2_rx_subsyst_1 0x84A2_0000
axi_iic_mipi 0x84A4_0000
v_frmbuf_wr_0 0x84A6_0000
v_frmbuf_wr_1 0x84A8_0000
v_frmbuf_wr_2 0x84AA_0000
v_frmbuf_wr_3 0x84AC_0000
v_frmbuf_wr_4 0x84AE_0000
v_frmbuf_wr_5 0x84B0_0000
v_frmbuf_wr_6 0x84B2_0000
v_frmbuf_wr_7 0x84B4_0000
axi_pwm_gen_0 0x84B6_0000
corundum_hierarchy/corundum_core/s_axil_ctrl 0xA000_0000
============================================ ===========

I2C connections
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Expand Down Expand Up @@ -211,7 +210,7 @@ v_frmbuf_wr4/interrupt 8 104 136
v_frmbuf_wr5/interrupt 7 96 128
v_frmbuf_wr6/interrupt 6 95 127
v_frmbuf_wr7/interrupt 5 94 126
combined_corundum_irq 4 93 125
corundum_hierarcy/irq 4 93 125
======================= === ============ =============

Building the HDL project
Expand All @@ -225,7 +224,7 @@ If you want to build the sources, ADI makes them available on the
`clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__
the HDL repository, and then build the project as follows:.

This project uses `Corundum NIC <https://github.com/corundum/corundum>`_
This project uses `Corundum NIC <https://github.com/ucsdsysnet/corundum>`_
and it needs to be cloned alongside this repository.

.. admonition:: Publications
Expand All @@ -243,9 +242,7 @@ and it needs to be cloned alongside this repository.
**Linux/Cygwin/WSL**

.. shell::

$git clone https://github.com/corundum/corundum.git
$git checkout ed4a26e2cbc0a429c45d5cd5ddf1177f86838914
====================://github.com/ucsdsysnet/corundum.git
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HTML build issue:
index.rst:244: ERROR: Content block expected for the "shell" directive; none found.
index.rst:245: WARNING: Explicit markup ends without a blank line; unexpected unindent.

$cd hdl/projects/ad_gmsl2eth_sl/k26
$make

Expand Down Expand Up @@ -289,7 +286,7 @@ HDL related
* - AXI_SYSID
- :git-hdl:`library/axi_sysid`
- :ref:`axi_sysid`
* - CORUNDUM
* - CORUNDUM_NETSTACK
- :git-hdl:`library/corundum`
- :ref:`corundum`
* - SYSID_ROM
Expand Down
117 changes: 108 additions & 9 deletions library/corundum/ethernet/Makefile
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CMAC dependencies should be left so that the make can verify their existence if 100G needs to be built.
Remove dependencies that are not related to the Ethernet core's build.

Original file line number Diff line number Diff line change
Expand Up @@ -2,19 +2,116 @@ LIBRARY_NAME := ethernet

XILINX_DEPS += ethernet_ip.tcl

EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_port_map_mac_axis.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/lib/axis/rtl/sync_reset.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/cmac_gty_wrapper.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/cmac_gty_ch_wrapper.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/rb_drp.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/cmac_pad.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mac_ts_insert.v
GENERIC_DEPS += ethernet_core_k26.v
GENERIC_DEPS += ethernet_core_vcu118.v

EXTERNAL_DEPS += ../../../../corundum/fpga/mqnic/VCU118/fpga_100g/ip/cmac_usplus.tcl
EXTERNAL_DEPS += ../../../../corundum/fpga/mqnic/VCU118/fpga_100g/ip/cmac_gty.tcl
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_core_axi.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_core.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_dram_if.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_interface.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_interface_tx.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_interface_rx.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_port.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_port_tx.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_port_rx.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_egress.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_ingress.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_l2_egress.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_l2_ingress.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_rx_queue_map.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_ptp.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_ptp_clock.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_ptp_perout.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_rb_clk_info.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_port_map_phy_xgmii.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/cpl_write.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/cpl_op_mux.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/desc_fetch.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/desc_op_mux.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/queue_manager.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/cpl_queue_manager.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/tx_fifo.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/rx_fifo.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/tx_req_mux.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/tx_engine.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/rx_engine.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/tx_checksum.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/rx_hash.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/rx_checksum.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/rb_drp.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/stats_counter.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/stats_collect.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/stats_dma_if_axi.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/stats_dma_latency.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_tx_scheduler_block_rr.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/tx_scheduler_rr.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/tdma_scheduler.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/tdma_ber.v
EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/tdma_ber_ch.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/eth_mac_10g.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/axis_xgmii_rx_64.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/axis_xgmii_rx_32.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/axis_xgmii_tx_64.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/axis_xgmii_tx_32.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/mac_ctrl_rx.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/mac_ctrl_tx.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/mac_pause_ctrl_rx.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/mac_pause_ctrl_tx.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/lfsr.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/ptp_clock.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/ptp_clock_cdc.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/ptp_perout.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/axi/rtl/axil_interconnect.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/axi/rtl/axil_crossbar.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/axi/rtl/axil_crossbar_addr.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/axi/rtl/axil_crossbar_rd.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/axi/rtl/axil_crossbar_wr.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/axi/rtl/axil_reg_if.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/axi/rtl/axil_reg_if_rd.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/axi/rtl/axil_reg_if_wr.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/axi/rtl/axil_register_rd.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/axi/rtl/axil_register_wr.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/axi/rtl/arbiter.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/axi/rtl/priority_encoder.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/lib/axis/rtl/sync_reset.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/lib/axis/rtl/axis_adapter.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/lib/axis/rtl/axis_arb_mux.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/lib/axis/rtl/axis_demux.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/lib/axis/rtl/axis_fifo.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/lib/axis/rtl/axis_fifo_adapter.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/lib/axis/rtl/axis_pipeline_fifo.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/lib/axis/rtl/axis_register.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/pcie/rtl/irq_rate_limit.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/pcie/rtl/dma_if_axi.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/pcie/rtl/dma_if_axi_rd.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/pcie/rtl/dma_if_axi_wr.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/pcie/rtl/dma_if_mux.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/pcie/rtl/dma_if_mux_rd.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/pcie/rtl/dma_if_mux_wr.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/pcie/rtl/dma_if_desc_mux.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/pcie/rtl/dma_ram_demux_rd.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/pcie/rtl/dma_ram_demux_wr.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/pcie/rtl/dma_psdpram.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/pcie/rtl/dma_client_axis_sink.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/pcie/rtl/dma_client_axis_source.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/pcie/rtl/pulse_merge.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/eth_phy_10g_tx_if.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/eth_phy_10g_tx.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/eth_phy_10g_rx.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/eth_phy_10g.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/eth_phy_10g_rx_if.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/eth_phy_10g_rx_watchdog.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/xgmii_baser_dec_64.v
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/xgmii_baser_enc_64.v

XILINX_DEPS += ../interfaces/if_ctrl_reg.xml
XILINX_DEPS += ../interfaces/if_ctrl_reg_rtl.xml
XILINX_DEPS += ../interfaces/if_csr.xml
XILINX_DEPS += ../interfaces/if_csr_rtl.xml
XILINX_DEPS += ../interfaces/if_ptp.xml
XILINX_DEPS += ../interfaces/if_ptp_rtl.xml
XILINX_DEPS += ../interfaces/if_flow_control_tx.xml
Expand All @@ -29,6 +126,8 @@ XILINX_DEPS += ../interfaces/if_qspi.xml
XILINX_DEPS += ../interfaces/if_qspi_rtl.xml
XILINX_DEPS += ../interfaces/if_qsfp.xml
XILINX_DEPS += ../interfaces/if_qsfp_rtl.xml
XILINX_DEPS += ../interfaces/if_sfp.xml
XILINX_DEPS += ../interfaces/if_sfp_rtl.xml
XILINX_DEPS += ../interfaces/if_i2c.xml
XILINX_DEPS += ../interfaces/if_i2c_rtl.xml

Expand Down
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