AXI SPI Engine offload optimization #2757
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In order to achieve a 4 MSPS rate on a 16-bit ADC with a 80 MHz SCLK using the SPI offload feature of the AXI SPI engine, we need to shave off some time that is spent executing unnecessary instructions. There are a few one-time setup instructions that can be moved so that they execute only once when the SPI offload trigger is enabled rather than repeating each time the offload is triggered. Additionally, a change to IP block allows dropping the SYNC instruction completely. With these changes, we are left with only the 3 instructions that are needed to to assert CS, transfer the data, and deassert CS. This makes 3 + 16 * 12.5 ns = 237.5 ns < 250 ns which is within the available time (time needed for 3 instructions + 16 SCLK cycles). # Describe the purpose of this series. The information you put here # will be used by the project maintainer to make a decision whether # your patches should be reviewed, and in what priority order. Please be # very detailed and link to any relevant discussions or sites that the # maintainer can review to better understand your proposed changes. If you # only have a single patch in your series, the contents of the cover # letter will be appended to the "under-the-cut" portion of the patch. # Lines starting with # will be removed from the cover letter. You can # use them to add notes or reminders to yourself. If you want to use # markdown headers in your cover letter, start the line with ">#". # You can add trailers to the cover letter. Any email addresses found in # these trailers will be added to the addresses specified/generated # during the b4 send stage. You can also run "b4 prep --auto-to-cc" to # auto-populate the To: and Cc: trailers based on the code being # modified. Signed-off-by: David Lechner <[email protected]> --- b4-submit-tracking --- # This section is used internally by b4 prep for tracking purposes. { "series": { "revision": 1, "change-id": "20250331-adi-main-46863acfc540", "prefixes": [] } }
Add a polling wait for SPI instruction execution to complete in the spi_engine_setup() function. In practice, these instructions complete in a few 10s of nanoseconds, so we never ran into any race conditions, but it is good practice to wait for the completion of the SPI engine instructions before returning from the setup function. Signed-off-by: David Lechner <[email protected]>
Add an optimization to avoid repeating the config instruction in each SPI message when using SPI offloading. Instead, the instruction is run once when the SPI offload trigger is enabled. This is done to allow higher sample rates for ADCs using this SPI controller. Signed-off-by: David Lechner <[email protected]>
Add an optimization to avoid repeating bits_per_word instructions in each message when using SPI offload. This only applies when all data xfers in a message have the same bits_per_word. In this case, we can execute the instruction that sets bits_per_word when the offload trigger is enabled. This is useful e.g. for obtaining higher sample rates on ADCs since each message takes less time to execute. Signed-off-by: David Lechner <[email protected]>
Add optimization to omit SYNC instructions from offload messages. Starting with IP core v1.5.0, the SYNC instruction is no longer required for proper operation when using the offload feature. Omitting the SYNC instruction saves a few clock cycles needed to executed which can e.g. allow achieving higher sample rates on ADCs. Signed-off-by: David Lechner <[email protected]>
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PR Description
This contains some optimizations that are needed to be able to obtain 4 MSPS, e.g. on AD738x.
I'm marking this a a draft since this needs to be upstreamed first and there are a few HDL things to finalize to make sure everything is working correctly. But feel free to do a pre-review before I send it upstream.
Related PR that bumps SPI Engine IP core version to 1.5: analogdevicesinc/hdl#1637 (comment)
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