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Code taken from https://github.com/petrpavlu/valgrind-riscv64 Some minor adjustments have been made because that code is based on upstream libvex.
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| /*--------------------------------------------------------------------*/ | ||
| /*--- begin guest_riscv64_defs.h ---*/ | ||
| /*--------------------------------------------------------------------*/ | ||
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| /* | ||
| This file is part of Valgrind, a dynamic binary instrumentation | ||
| framework. | ||
| Copyright (C) 2020-2023 Petr Pavlu | ||
| [email protected] | ||
| This program is free software; you can redistribute it and/or | ||
| modify it under the terms of the GNU General Public License as | ||
| published by the Free Software Foundation; either version 2 of the | ||
| License, or (at your option) any later version. | ||
| This program is distributed in the hope that it will be useful, but | ||
| WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
| General Public License for more details. | ||
| You should have received a copy of the GNU General Public License | ||
| along with this program; if not, see <http://www.gnu.org/licenses/>. | ||
| The GNU General Public License is contained in the file COPYING. | ||
| Neither the names of the U.S. Department of Energy nor the | ||
| University of California nor the names of its contributors may be | ||
| used to endorse or promote products derived from this software | ||
| without prior written permission. | ||
| */ | ||
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| /* Only to be used within the guest_riscv64_* files. */ | ||
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| #ifndef __VEX_GUEST_RISCV64_DEFS_H | ||
| #define __VEX_GUEST_RISCV64_DEFS_H | ||
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| #include "libvex_basictypes.h" | ||
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| #include "guest_generic_bb_to_IR.h" | ||
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| /*------------------------------------------------------------*/ | ||
| /*--- riscv64 to IR conversion ---*/ | ||
| /*------------------------------------------------------------*/ | ||
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| /* Convert one riscv64 insn to IR. See the type DisOneInstrFn in | ||
| guest_generic_bb_to_IR.h. */ | ||
| DisResult disInstr_RISCV64(IRSB* irbb, | ||
| const UChar* guest_code, | ||
| Long delta, | ||
| Addr guest_IP, | ||
| VexArch guest_arch, | ||
| const VexArchInfo* archinfo, | ||
| const VexAbiInfo* abiinfo, | ||
| VexEndness host_endness, | ||
| Bool sigill_diag); | ||
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| /* Used by the optimiser to specialise calls to helpers. */ | ||
| IRExpr* guest_riscv64_spechelper(const HChar* function_name, | ||
| IRExpr** args, | ||
| IRStmt** precedingStmts, | ||
| Int n_precedingStmts); | ||
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| /* Describes to the optimiser which part of the guest state require precise | ||
| memory exceptions. This is logically part of the guest state description. */ | ||
| Bool guest_riscv64_state_requires_precise_mem_exns( | ||
| Int minoff, Int maxoff, VexRegisterUpdates pxControl); | ||
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| extern VexGuestLayout riscv64guest_layout; | ||
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| /*------------------------------------------------------------*/ | ||
| /*--- riscv64 guest helpers ---*/ | ||
| /*------------------------------------------------------------*/ | ||
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| /* --- CLEAN HELPERS --- */ | ||
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| /* Calculate resulting flags of a specified floating-point operation. Returns | ||
| a 32-bit value where bits 4:0 contain the fflags in the RISC-V native | ||
| format (NV DZ OF UF NX) and remaining upper bits are zero. */ | ||
| UInt riscv64g_calculate_fflags_fsqrt_s(Float a1, UInt rm_RISCV); | ||
| UInt riscv64g_calculate_fflags_fcvt_w_s(Float a1, UInt rm_RISCV); | ||
| UInt riscv64g_calculate_fflags_fcvt_wu_s(Float a1, UInt rm_RISCV); | ||
| UInt riscv64g_calculate_fflags_fcvt_s_w(UInt a1, UInt rm_RISCV); | ||
| UInt riscv64g_calculate_fflags_fcvt_s_wu(UInt a1, UInt rm_RISCV); | ||
| UInt riscv64g_calculate_fflags_fcvt_l_s(Float a1, UInt rm_RISCV); | ||
| UInt riscv64g_calculate_fflags_fcvt_lu_s(Float a1, UInt rm_RISCV); | ||
| UInt riscv64g_calculate_fflags_fcvt_s_l(ULong a1, UInt rm_RISCV); | ||
| UInt riscv64g_calculate_fflags_fcvt_s_lu(ULong a1, UInt rm_RISCV); | ||
| UInt riscv64g_calculate_fflags_fsqrt_d(Double a1, UInt rm_RISCV); | ||
| UInt riscv64g_calculate_fflags_fcvt_s_d(Double a1, UInt rm_RISCV); | ||
| UInt riscv64g_calculate_fflags_fcvt_w_d(Double a1, UInt rm_RISCV); | ||
| UInt riscv64g_calculate_fflags_fcvt_wu_d(Double a1, UInt rm_RISCV); | ||
| UInt riscv64g_calculate_fflags_fcvt_l_d(Double a1, UInt rm_RISCV); | ||
| UInt riscv64g_calculate_fflags_fcvt_lu_d(Double a1, UInt rm_RISCV); | ||
| UInt riscv64g_calculate_fflags_fcvt_d_l(ULong a1, UInt rm_RISCV); | ||
| UInt riscv64g_calculate_fflags_fcvt_d_lu(ULong a1, UInt rm_RISCV); | ||
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| UInt riscv64g_calculate_fflags_fadd_s(Float a1, Float a2, UInt rm_RISCV); | ||
| UInt riscv64g_calculate_fflags_fmul_s(Float a1, Float a2, UInt rm_RISCV); | ||
| UInt riscv64g_calculate_fflags_fdiv_s(Float a1, Float a2, UInt rm_RISCV); | ||
| UInt riscv64g_calculate_fflags_fadd_d(Double a1, Double a2, UInt rm_RISCV); | ||
| UInt riscv64g_calculate_fflags_fmul_d(Double a1, Double a2, UInt rm_RISCV); | ||
| UInt riscv64g_calculate_fflags_fdiv_d(Double a1, Double a2, UInt rm_RISCV); | ||
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| UInt riscv64g_calculate_fflags_fmin_s(Float a1, Float a2); | ||
| UInt riscv64g_calculate_fflags_fmax_s(Float a1, Float a2); | ||
| UInt riscv64g_calculate_fflags_feq_s(Float a1, Float a2); | ||
| UInt riscv64g_calculate_fflags_flt_s(Float a1, Float a2); | ||
| UInt riscv64g_calculate_fflags_fle_s(Float a1, Float a2); | ||
| UInt riscv64g_calculate_fflags_fmin_d(Double a1, Double a2); | ||
| UInt riscv64g_calculate_fflags_fmax_d(Double a1, Double a2); | ||
| UInt riscv64g_calculate_fflags_feq_d(Double a1, Double a2); | ||
| UInt riscv64g_calculate_fflags_flt_d(Double a1, Double a2); | ||
| UInt riscv64g_calculate_fflags_fle_d(Double a1, Double a2); | ||
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| UInt riscv64g_calculate_fflags_fmadd_s(Float a1, | ||
| Float a2, | ||
| Float a3, | ||
| UInt rm_RISCV); | ||
| UInt riscv64g_calculate_fflags_fmadd_d(Double a1, | ||
| Double a2, | ||
| Double a3, | ||
| UInt rm_RISCV); | ||
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| /* Calculate floating-point class. Returns a 64-bit value where bits 9:0 | ||
| contains the properties in the RISC-V FCLASS-instruction format and remaining | ||
| upper bits are zero. */ | ||
| ULong riscv64g_calculate_fclass_s(Float a1); | ||
| ULong riscv64g_calculate_fclass_d(Double a1); | ||
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| #endif /* ndef __VEX_GUEST_RISCV64_DEFS_H */ | ||
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| /*--------------------------------------------------------------------*/ | ||
| /*--- end guest_riscv64_defs.h ---*/ | ||
| /*--------------------------------------------------------------------*/ |
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