HAL: Add PMC, EFC configuration APIs

Cargo.toml

@@ -1,5 +1,8 @@
-[workspace]
-members = [
-    "hal",
-    "pac/*",
-]
+[workspace]
+members = [
+    "hal",
+    "pac/*",
+]
+exclude = [
+  "boards/atsame70_xpro"
+]

boards/.gitignore

@@ -0,0 +1 @@
+**/Cargo.lock

boards/atsame70_xpro/.cargo/config

@@ -0,0 +1,8 @@
+[target.thumbv7em-none-eabihf]
+runner = "arm-none-eabi-gdb -q -x openocd.gdb"
+
+[build]
+target = "thumbv7em-none-eabihf"
+rustflags = [
+  "-C", "link-arg=-Tlink.x",
+]

boards/atsame70_xpro/Cargo.toml

@@ -0,0 +1,22 @@
+[package]
+name = "atsame70_xpro"
+version = "0.1.0"
+edition = "2021"
+authors = [
+    "Viktor Sonesten <[email protected]>"
+]
+license = "0BSD"
+
+[dependencies]
+cortex-m-rtic = "1.0"
+cortex-m = "0.7"
+panic-halt = "0.2"
+
+[dependencies.atsamx7x-hal]
+version = "0.1.0"
+path = "../../hal"
+features = ["same70q21b-rt"]
+
+[profile.dev]
+debug = true
+lto = true

boards/atsame70_xpro/README.md

@@ -0,0 +1,31 @@
+# SAM E70 Xplained Pro Evaluation Kit examples
+
+This crate provides HAL usage examples for working with the [SAM E70 Xplained Pro Evaulation Kit](https://www.microchip.com/en-us/development-tool/DM320113).
+The examples are written in [RTIC](https://rtic.rs).
+
+## Prerequisites
+* Install the cross-compilation toolchain: `rustup target add thumbv7em-none-eabihf`.
+* Install [openocd `v0.11.0`](https://openocd.org/openocd-0-11-0-released.html) (or above).
+
+## Flashing an example
+First, the General-Purpose Non-Volatile-Memory (GPNVM) boot bit must be set in order to map the flashed firmware to address `0x0`;
+required for the interrupts and software resets to work as expected:
+1. Connect the board via the "Debug USB" port and run
+   ```shell
+   $ openocd -f openocd.cfg -c "atsamv gpnvm set 1" -c exit
+   ```
+2. Power-cycle the board, and the verify with
+   ```shell
+   $ openocd -f openocd.cfg -c "atsamv gpnvm show 1" -c exit
+   [...]
+   samv-gpnvm1: 1
+   ```
+
+The example can now be flashed after first, in a seperate shell, `openocd -f openocd.cfg`
+```shell
+$ cargo run
+```
+
+## Erasing bad firmware
+In case the board has been flashed with software that sets it in a bad state before the debugger can attach, bridge the "ERASE" header (J400; north of the MCU) between power cycles, and remove the bridge.
+The flash area has now been zeroed.

boards/atsame70_xpro/memory.x

@@ -0,0 +1,31 @@
+MEMORY
+{
+  FLASH : ORIGIN = 0x400000, LENGTH = 2M
+  RAM : ORIGIN = 0x20400000, LENGTH = 256K /* 256K or 384K; p. 54 */
+}
+
+/* This is where the call stack will be allocated. */
+/* The stack is of the full descending type. */
+/* You may want to use this variable to locate the call stack and static
+   variables in different memory regions. Below is shown the default value */
+/* _stack_start = ORIGIN(RAM) + LENGTH(RAM); */
+
+/* You can use this symbol to customize the location of the .text section */
+/* If omitted the .text section will be placed right after the .vector_table
+   section */
+/* This is required only on microcontrollers that store some configuration right
+   after the vector table */
+/* _stext = ORIGIN(FLASH) + 0x400; */
+
+/* Example of putting non-initialized variables into custom RAM locations. */
+/* This assumes you have defined a region RAM2 above, and in the Rust
+   sources added the attribute `#[link_section = ".ram2bss"]` to the data
+   you want to place there. */
+/* Note that the section will not be zero-initialized by the runtime! */
+/* SECTIONS {
+     .ram2bss (NOLOAD) : ALIGN(4) {
+       *(.ram2bss);
+       . = ALIGN(4);
+     } > RAM2
+   } INSERT AFTER .bss;
+*/

boards/atsame70_xpro/openocd.cfg

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+source [find interface/cmsis-dap.cfg]
+set CHIPNAME atsame70n21
+source [find target/atsamv.cfg]
+
+init
+reset halt

boards/atsame70_xpro/openocd.gdb

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+target extended-remote :3333
+
+set print asm-demangle on
+
+# detect unhandled exceptions, hard faults and panics
+break DefaultHandler
+break HardFault
+break rust_begin_unwind
+
+# *try* to stop at the user entry point (it might be gone due to inlining)
+# break main
+
+monitor arm semihosting enable
+monitor halt
+
+load
+
+# start the process but immediately halt the processor
+stepi
+
+# Helpers
+define reload
+  monitor reset halt
+  continue
+end
+
+define reflash
+  !cargo build
+  monitor reset halt
+  load
+  continue
+end
+
+alias rl = reload
+alias rf = reflash

boards/atsame70_xpro/src/main.rs

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+#![no_std]
+#![no_main]
+
+use panic_halt as _;
+
+#[rtic::app(device = atsamx7x_hal::target_device, peripherals = true, dispatchers = [IXC])]
+mod app {
+    use atsamx7x_hal as hal;
+    use hal::ehal::watchdog::WatchdogDisable;
+
+    #[shared]
+    struct Shared {}
+
+    #[local]
+    struct Local {}
+
+    #[init]
+    fn init(mut ctx: init::Context) -> (Shared, Local, init::Monotonics) {
+        cortex_m::asm::bkpt();
+
+        // Disable the watchdog.
+        hal::watchdog::Watchdog::new(ctx.device.WDT).disable();
+
+        let mut efc = {
+            use hal::efc::{Efc, VddioLevel};
+            Efc::new(ctx.device.EFC, VddioLevel::V3)
+        };
+
+        // Configure the clock hierarchy
+        {
+            use hal::pmc::{
+                HostClockConfig, MainCkSource, MckDivider, MckPrescaler, Megahertz, PckId,
+                PllaConfig, Pmc, UpllDivider,
+            };
+
+            let mut pmc = Pmc::new(ctx.device.PMC);
+            let mainck = pmc
+                .get_mainck(MainCkSource::ExternalBypass(Megahertz::from_raw(12)))
+                .unwrap();
+            let _plla = pmc
+                .get_pllack(PllaConfig { div: 1, mult: 8 }, &mainck)
+                .unwrap();
+            let _hclk = pmc
+                .get_hclk(
+                    HostClockConfig {
+                        pres: MckPrescaler::CLK_1,
+                        div: MckDivider::EQ_PCK,
+                    },
+                    &mainck,
+                    &mut efc,
+                )
+                .unwrap();
+
+            let upllck = pmc.get_upllck(&mainck, &mut ctx.device.UTMI).unwrap();
+            let upllckdiv = pmc.get_upllckdiv(&upllck, UpllDivider::Div2);
+            let _pck2 = pmc.get_pck(&upllckdiv, 100 - 1, PckId::Pck2); // @ 2.4MHz
+        }
+
+        // Configure PA03 as PCK2 output
+        {
+            let pioa = ctx.device.PIOA;
+
+            // Configure pins for function C: UART4 (0b10)
+            pioa.pio_abcdsr[1].modify(|_, w| w.p3().set_bit());
+            pioa.pio_abcdsr[0].modify(|_, w| w.p3().clear_bit());
+
+            // Give pins to the peripheral.
+            pioa.pio_pdr.write(|w| w.p3().set_bit());
+            cortex_m::asm::dsb();
+            assert!(pioa.pio_psr.read().p3().bit_is_clear());
+
+            // disable multidrive
+            pioa.pio_mddr.write(|w| w.p3().set_bit());
+            cortex_m::asm::dsb();
+            assert!(pioa.pio_mdsr.read().p3().bit_is_clear());
+
+            // ensure we dont pull the pin up/down
+            pioa.pio_pudr.write(|w| w.p3().set_bit());
+            pioa.pio_ppddr.write(|w| w.p3().set_bit());
+            cortex_m::asm::dsb();
+            assert!(pioa.pio_pusr.read().p3().bit_is_set());
+            assert!(pioa.pio_ppdsr.read().p3().bit_is_set());
+        }
+
+        (Shared {}, Local {}, init::Monotonics())
+    }
+
+    #[idle]
+    fn idle(_: idle::Context) -> ! {
+        loop {
+            cortex_m::asm::nop();
+        }
+    }
+}