Clang format

.github/workflows/misc-tests.yaml

@@ -121,3 +121,29 @@ jobs:
       - if: ${{ matrix.os != 'windows-latest' }}
         name: Run tests
         run: cmake --build "path has spaces/build-fips" --target run_tests
+  clang-format:
+    if: github.repository_owner == 'aws'
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v2
+      - name: Install clang-format
+        run: |
+          sudo apt-get update
+          sudo apt-get install -y clang-format-17
+          sudo update-alternatives --display clang-format
+          # Register alternatives
+          sudo update-alternatives --install /usr/bin/clang-format clang-format /usr/bin/clang-format-17 100
+          sudo update-alternatives --install /usr/bin/clang-format clang-format /usr/bin/clang-format-18 50
+          # Set preferred version
+          sudo update-alternatives --set clang-format /usr/bin/clang-format-17
+          # Verify the version
+          clang-format --version
+      - name: Check formatting
+        run: |
+          clang-format --version
+          ./util/check_clang_format.sh --check
+      - name: Formatting instructions
+        if: failure()
+        run: |
+          echo "Formatting issues found. To fix locally, run:"
+          echo "  ./util/check_clang_format.sh --fix"

include/openssl/aead.h

@@ -435,10 +435,7 @@ OPENSSL_EXPORT const EVP_AEAD *EVP_aead_aes_256_gcm_tls13(void);
 // Obscure functions.
 
 // evp_aead_direction_t denotes the direction of an AEAD operation.
-enum evp_aead_direction_t {
-  evp_aead_open,
-  evp_aead_seal
-};
+enum evp_aead_direction_t { evp_aead_open, evp_aead_seal };
 
 // EVP_AEAD_CTX_init_with_direction calls |EVP_AEAD_CTX_init| for normal
 // AEADs. For TLS-specific and SSL3-specific AEADs, it initializes |ctx| for a

include/openssl/arm_arch.h

@@ -80,7 +80,7 @@
 #define ARMV8_SHA512 (1 << 6)
 
 // ARMV8_SHA3 indicates support for hardware SHA-3 instructions including EOR3.
-#define ARMV8_SHA3  (1 << 11)
+#define ARMV8_SHA3 (1 << 11)
 
 // The Neoverse V1, V2, and Apple M1 micro-architectures are detected to enable
 // high unrolling factor of AES-GCM and other algorithms that leverage a
@@ -108,40 +108,36 @@
 // |____ _ _____|_____ _ _____|_________|_______ _|____ _ ___|________|
 //
 
-# define ARM_CPU_IMP_ARM           0x41
+#define ARM_CPU_IMP_ARM 0x41
 
-# define ARM_CPU_PART_CORTEX_A72   0xD08
-# define ARM_CPU_PART_N1           0xD0C
-# define ARM_CPU_PART_V1           0xD40
-# define ARM_CPU_PART_V2           0xD4F
+#define ARM_CPU_PART_CORTEX_A72 0xD08
+#define ARM_CPU_PART_N1 0xD0C
+#define ARM_CPU_PART_V1 0xD40
+#define ARM_CPU_PART_V2 0xD4F
 
-# define MIDR_PARTNUM_SHIFT       4
-# define MIDR_PARTNUM_MASK        (0xfffUL << MIDR_PARTNUM_SHIFT)
-# define MIDR_PARTNUM(midr)       \
-           (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
+#define MIDR_PARTNUM_SHIFT 4
+#define MIDR_PARTNUM_MASK (0xfffUL << MIDR_PARTNUM_SHIFT)
+#define MIDR_PARTNUM(midr) (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
 
-# define MIDR_IMPLEMENTER_SHIFT   24
-# define MIDR_IMPLEMENTER_MASK    (0xffUL << MIDR_IMPLEMENTER_SHIFT)
-# define MIDR_IMPLEMENTER(midr)   \
-           (((midr) & MIDR_IMPLEMENTER_MASK) >> MIDR_IMPLEMENTER_SHIFT)
+#define MIDR_IMPLEMENTER_SHIFT 24
+#define MIDR_IMPLEMENTER_MASK (0xffUL << MIDR_IMPLEMENTER_SHIFT)
+#define MIDR_IMPLEMENTER(midr) \
+  (((midr) & MIDR_IMPLEMENTER_MASK) >> MIDR_IMPLEMENTER_SHIFT)
 
-# define MIDR_ARCHITECTURE_SHIFT  16
-# define MIDR_ARCHITECTURE_MASK   (0xfUL << MIDR_ARCHITECTURE_SHIFT)
-# define MIDR_ARCHITECTURE(midr)  \
-           (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
+#define MIDR_ARCHITECTURE_SHIFT 16
+#define MIDR_ARCHITECTURE_MASK (0xfUL << MIDR_ARCHITECTURE_SHIFT)
+#define MIDR_ARCHITECTURE(midr) \
+  (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
 
-# define MIDR_CPU_MODEL_MASK \
-           (MIDR_IMPLEMENTER_MASK | \
-            MIDR_PARTNUM_MASK     | \
-            MIDR_ARCHITECTURE_MASK)
+#define MIDR_CPU_MODEL_MASK \
+  (MIDR_IMPLEMENTER_MASK | MIDR_PARTNUM_MASK | MIDR_ARCHITECTURE_MASK)
 
-# define MIDR_CPU_MODEL(imp, partnum) \
-           (((imp)     << MIDR_IMPLEMENTER_SHIFT)  | \
-            (0xfUL       << MIDR_ARCHITECTURE_SHIFT) | \
-            ((partnum) << MIDR_PARTNUM_SHIFT))
+#define MIDR_CPU_MODEL(imp, partnum)                                        \
+  (((imp) << MIDR_IMPLEMENTER_SHIFT) | (0xfUL << MIDR_ARCHITECTURE_SHIFT) | \
+   ((partnum) << MIDR_PARTNUM_SHIFT))
 
-# define MIDR_IS_CPU_MODEL(midr, imp, partnum) \
-           (((midr) & MIDR_CPU_MODEL_MASK) == MIDR_CPU_MODEL(imp, partnum))
+#define MIDR_IS_CPU_MODEL(midr, imp, partnum) \
+  (((midr) & MIDR_CPU_MODEL_MASK) == MIDR_CPU_MODEL(imp, partnum))
 
 #endif  // ARM || AARCH64
 

include/openssl/asm_base.h

@@ -40,12 +40,14 @@
 
 #include <openssl/boringssl_prefix_symbols_asm.h>
 
+// clang-format off
 #if defined(__ELF__)
 // Every ELF object file, even empty ones, should disable executable stacks. See
 // https://www.airs.com/blog/archives/518.
 .pushsection .note.GNU-stack, "", %progbits
 .popsection
 #endif
+// clang-format on
 
 #if defined(__CET__) && defined(OPENSSL_X86_64)
 // Clang and GCC define __CET__ and provide <cet.h> when they support Intel's
@@ -183,6 +185,7 @@
 #define AARCH64_VALIDATE_LINK_REGISTER
 #endif
 
+// clang-format off
 #if GNU_PROPERTY_AARCH64_POINTER_AUTH != 0 || GNU_PROPERTY_AARCH64_BTI != 0
 .pushsection .note.gnu.property, "a";
 .balign 8;
@@ -196,6 +199,7 @@
 .long 0;
 .popsection;
 #endif
+// clang-format on
 #endif  // ARM || AARCH64
 
 #endif  // __ASSEMBLER__