Brian Bui briann-bui

👨‍💻 About Me

_{Who I am and what I focus on as a digital design engineer.}

I'm Bui Minh Nhut (Brian Bui), a digital design engineer focused on turning specifications into clean, synthesizable, and reusable RTL.

⚙️ Design SoC and MCU IP using Verilog and SystemVerilog
🔌 Build memory-mapped peripherals with AMBA APB and AXI4-Lite interfaces
🛡️ Develop self-checking testbenches and UVM verification environments
🚀 Work across the RTL flow: architecture, coding, lint, simulation, debug, and documentation
🔬 Explore cryptographic accelerators, processor subsystems, FPGA prototyping, and design automation

_{RTL IP cores and tools, from architecture through verification.}

📦 Project	💡 Highlights	🛠️ Technologies
SHA-256 Core	Modular SHA-256 RTL core supporting single- and multi-block hashing with reusable verification infrastructure	`SystemVerilog` `UVM` `Synopsys VCS`
AES-256 Core	Synthesizable AES-256 accelerator with AXI4-Lite control, multiple operating modes, interrupts, and UVM verification	`SystemVerilog` `UVM` `AXI4-Lite`
APB SPI Master	FIFO-buffered SPI Master Controller IP with APB interface, multi-mode support, and UVM verification	`SystemVerilog` `UVM` `AMBA APB`
APB Watchdog	Synthesizable Watchdog Timer IP core with APB interface, cascaded counters, and interrupt/reset generation	`SystemVerilog` `UVM` `AMBA APB`
APB RTC Core	Binary Gregorian calendar with programmable prescaler, date-qualified alarm, sticky interrupts, and UVM verification	`SystemVerilog` `UVM` `AMBA APB`
APB NTT Core	Radix-2 forward NTT accelerator with internal coefficient memory for post-quantum cryptography research	`SystemVerilog` `UVM` `AMBA APB`
APB PIC Core	Configurable priority arbitration and claim/complete flow for Cortex-M and RISC-V subsystem integration	`SystemVerilog` `UVM` `AMBA APB`
APB TRNG Core	GF180 ring-oscillator entropy source with health monitoring, SHA-256 conditioning, FIFO buffering, and UVM verification	`SystemVerilog` `UVM` `GF180` `AMBA APB`

_{The EDA toolchain and engineering stack behind the projects above.}

OpenLane _{RTL-to-GDSII Flow}	OpenROAD _{Physical Design}	Yosys _{RTL Synthesis}	Verilator _{Lint & Simulation}
Siemens EDA _{QuestaSim · ModelSim} _{HDL Simulation & Verification}	Synopsys EDA Suite _{VCS · Verdi · Design Compiler · SpyGlass · PrimeTime · PrimeWave} _{Simulation · Debug · Synthesis · Static Analysis · STA · AMS}		Quartus Prime _{FPGA Design & Synthesis}

Area	Technologies
🧬 RTL & Verification	Verilog, SystemVerilog, UVM, self-checking testbenches, functional coverage
🌉 Interfaces & Architecture	AMBA APB, AXI4-Lite, register maps, interrupts, FSMs, datapaths
🐞 Simulation & Quality	QuestaSim, ModelSim, VCS, Verdi, SpyGlass, Verilator, lint, waveform debug
🏗️ FPGA & ASIC	OpenLane, OpenROAD, Yosys, Design Compiler, PrimeTime, Intel Quartus, DRC/LVS
💻 Programming & Tools	Python, C/C++, Bash, Linux, Ubuntu, Git, VS Code

_{Six principles I follow to build reliable, maintainable, and integration-ready digital hardware.}

_{Clear naming, modular hierarchy, and code that communicates design intent.}	_{Well-defined protocols, timing expectations, register maps, and signal ownership.}	_{Predictable reset, state transitions, corner-case handling, and error responses.}
_{Parameterized, portable blocks designed for clean SoC and FPGA integration.}	_{Assertions, self-checking tests, coverage goals, and debug visibility from day one.}	_{Concise specifications, usage examples, diagrams, and reproducible workflows.}