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Final changes for BlackParrot integration #7

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d3a818c
OP local changes
Shashank-Vijay Jun 30, 2021
c4d8f32
Bumping BP submodule
Shashank-Vijay Jun 30, 2021
a509765
More changes
Shashank-Vijay Jul 9, 2021
9ded7e8
Minor changes
Shashank-Vijay Jul 9, 2021
c4c6e5f
Update sims,2.0
dpetrisko Jul 12, 2021
da77c23
Cosim module addition
Shashank-Vijay Jul 16, 2021
274a517
Working cacheable-only $readmemh memory for simulation
Jbalkind Jul 24, 2020
204f3e8
Various updates needed to run OP
dpetrisko Oct 3, 2021
5943677
Updating tcl scripts
dpetrisko Oct 4, 2021
5a2de3b
Moving blackparrot submodule
dpetrisko Oct 4, 2021
c48a5dd
Moving black-parrot submodule
dpetrisko Oct 4, 2021
85f552f
Use sdk environment variable
dpetrisko Oct 4, 2021
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2 changes: 1 addition & 1 deletion piton/design/chip/tile/blackparrot
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Submodule blackparrot updated 551 files
10 changes: 6 additions & 4 deletions piton/design/chipset/rtl/chipset_impl.v.pyv
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Original file line number Diff line number Diff line change
Expand Up @@ -946,8 +946,8 @@ uart_top uart_top (
`endif // PITONSYS_NO_MC

// Uncomment to connect to the switch
// .uart_timeout_en(uart_timeout_en),
.uart_timeout_en ( 1'b1 ),
.uart_timeout_en(uart_timeout_en),
// .uart_timeout_en ( 1'b1 ),
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@Jbalkind Jbalkind Aug 16, 2021

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What's the original for this? Would be good if this weren't changed versus upstream


.test_start ( test_start ),
.test_good_end ( test_good_end ),
Expand Down Expand Up @@ -1066,8 +1066,10 @@ ciop_fake_iob ciop_fake_iob(

<%
text = r'''
.spc0_inst_done (`PITON_CORE0_INST_DONE),
.pc_w0 (`PITON_CORE0_PC_W0),
`ifndef DISABLE_ALL_MONITORS
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@Jbalkind Jbalkind Aug 16, 2021

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Just remove the indent on this so it's a 2 line patch here

.spc0_inst_done (`PITON_CORE0_INST_DONE),
.pc_w0 (`PITON_CORE0_PC_W0),
`endif
'''

for i in range (PITON_NUM_TILES):
Expand Down
11 changes: 1 addition & 10 deletions piton/design/chipset/rtl/packet_filter.v.pyv
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Original file line number Diff line number Diff line change
Expand Up @@ -325,14 +325,6 @@ for i in range(1, len(devices)):

outputstr = """
else begin
`ifdef PITON_FPGA_SYNTH
// route everything else to the memory when uart_boot_en is asserted
if (%s (uart_boot_en)) begin
readdressed_flit0[`MSG_DST_X] = `NOC_X_WIDTH'h%x;
end else begin
invalid_access = 1'b1;
end
`else // PITON_FPGA_SYNTH
`ifdef MONITOR_INVALID_ACCESSES
// route everything else to the memory when uart_boot_en is asserted
if (%s (uart_boot_en)) begin
Expand All @@ -344,9 +336,8 @@ outputstr = """
// route everything else to the memory in simulation
readdressed_flit0[`MSG_DST_X] = `NOC_X_WIDTH'h%x;
`endif // MONITOR_INVALID_ACCESSES
`endif // PITON_FPGA_SYNTH
end
""" % (mem_addr_range, mem_port, mem_addr_range, mem_port, mem_port)
""" % (mem_addr_range, mem_port, mem_port)
print(outputstr)
%>
end
Expand Down
6 changes: 3 additions & 3 deletions piton/design/chipset/rtl/storage_addr_trans.v.pyv
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Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,7 @@ import pyhplib
import os
from pyhplib import *

if PITON_ARIANE:
if PITON_BLACKPARROT:
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@Jbalkind Jbalkind Aug 16, 2021

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This should probably just be the PITON_RV64_PLATFORM macro, right?

devices = pyhplib.ReadDevicesXMLFile()
%>

Expand All @@ -46,7 +46,7 @@ module storage_addr_trans #(parameter MEM_ADDR_WIDTH=64, VA_ADDR_WIDTH=40, STORA
output hit_any_section
);

`ifdef PITON_ARIANE
`ifdef PITON_BLACKPARROT

wire [63:0] storage_addr;

Expand All @@ -56,7 +56,7 @@ wire in_section_0;

// align physical address, and use correct memory offsets as specified in platform config
<%
if PITON_ARIANE:
if PITON_BLACKPARROT:
for i in range(len(devices)):
if devices[i]["name"] == "mem":
memBegin = devices[i]["base"]
Expand Down
6 changes: 3 additions & 3 deletions piton/design/chipset/rtl/storage_addr_trans_unified.v.pyv
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Expand Up @@ -33,7 +33,7 @@ import pyhplib
import os
from pyhplib import *

if PITON_ARIANE:
if PITON_BLACKPARROT:
devices = pyhplib.ReadDevicesXMLFile()
%>

Expand All @@ -46,7 +46,7 @@ module storage_addr_trans_unified #(parameter MEM_ADDR_WIDTH=64, VA_ADDR_WIDTH=4
output hit_any_section
);

`ifdef PITON_ARIANE
`ifdef PITON_BLACKPARROT

wire [63:0] storage_addr;

Expand All @@ -56,7 +56,7 @@ wire in_section_0;

// align physical address, and use correct memory offsets as specified in platform config
<%
if PITON_ARIANE:
if PITON_BLACKPARROT:
for i in range(len(devices)):
if devices[i]["name"] == "mem":
memBegin = devices[i]["base"]
Expand Down
3 changes: 3 additions & 0 deletions piton/design/xilinx/genesys2/constraints.xdc
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Expand Up @@ -58,6 +58,9 @@ set_false_path -from [get_ports trst_ni]
set_max_delay -datapath_only -from [get_clocks -include_generated_clocks chipset_clk_clk_mmcm] -to [get_clocks tck_i] 15.000
set_max_delay -datapath_only -from [get_clocks tck_i] -to [get_clocks -include_generated_clocks chipset_clk_clk_mmcm] 15.000

# Retiming
set_property BLOCK_SYNTH.RETIMING 1 [get_cells -hierarchical *pipe_fma*]

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@Jbalkind Jbalkind Aug 16, 2021

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This didn't end up helping much, right? Should we keep this out and wait for the manually retimed FPU?

set_property -dict {PACKAGE_PIN Y29 IOSTANDARD LVCMOS33} [get_ports trst_ni]
set_property -dict {PACKAGE_PIN AD27 IOSTANDARD LVCMOS33} [get_ports tck_i]
set_property -dict {PACKAGE_PIN W27 IOSTANDARD LVCMOS33} [get_ports td_i]
Expand Down
1 change: 1 addition & 0 deletions piton/tools/bin/rv64_img
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Expand Up @@ -27,6 +27,7 @@
# create mem.image
#riscv64-unknown-elf-objcopy --reverse-bytes 4 -I elf32-littleriscv -O binary diag.exe diag.o
${RV64_TARGET_TRIPLE}-objcopy -I elf64-littleriscv -O binary diag.exe diag.o
cp diag.exe prog.elf
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@Jbalkind Jbalkind Aug 16, 2021

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What is this for?

# pad with zero to 128byte boundary
du diag.o -b | awk '{print(128 - ($1 % 128));}' | xargs -t -ISIZE truncate diag.o -s +SIZE
printf "\n@0000000080000000\t// Section '.RED_SEC', segment 'text'\n" >mem.image
Expand Down
2 changes: 1 addition & 1 deletion piton/tools/src/proto/block.list
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Expand Up @@ -25,7 +25,7 @@
# Format:
# BlockID BlockPath Supported Board,Frequency(MHz),DDRSize(Mbytes)
piton_aws ../../build/f1/piton_aws/design f1,62.5,4096
system . vc707,60,1024;genesys2,66.667,1024;nexysVideo,30,512;vcu118,100,2048;xupp3r,60,32768
system . vc707,60,1024;genesys2,25,1024;nexysVideo,30,512;vcu118,100,2048;xupp3r,60,32768
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@Jbalkind Jbalkind Aug 16, 2021

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Still not excited about this - do we have a sense of the manually retimed FPU's timing?

chipset chipset genesys2,66.667,1024;piton_board,50,0
passthru passthru piton_board,100,0
passthru_loopback fpga_tests/passthru_loopback piton_board,100,0
Expand Down
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