fix the bug related to uart settings

07-ExterInterrupt/README.md

@@ -13,12 +13,32 @@ Press Ctrl-A and then X to exit QEMU
 qemu-system-riscv32 -nographic -smp 4 -machine virt -bios none -kernel os.elf
 OS start
 OS: Activate next task
-Hi!
+Task0: Created!
+Task0: Running...
+Task0: Running...
+Task0: Running...
+Task0: Running...
+Task0: Running...
+external interruption!
+j
+Task0: Running...
+Task0: Running...
+external interruption!
+k
+Task0: Running...
+Task0: Running...
+Task0: Running...
+external interruption!
+j
+Task0: Running...
+external interruption!
+k
+external interruption!
+j
+Task0: Running...
 timer interruption!
 timer_handler: 1
 OS: Back to OS
-
-OS: Activate next task
 QEMU: Terminated
 ```
 

07-ExterInterrupt/lib.c

@@ -1,7 +1,6 @@
 #include "lib.h"
 
 #define LSR_RX_READY (1 << 0)
-#define LSR_TX_IDLE (1 << 5)
 #define EOF 0
 
 void uart_init()

07-ExterInterrupt/os.c

@@ -2,6 +2,14 @@
 
 extern void trap_init(void);
 
+void panic(char *s)
+{
+	lib_puts(s);
+	for (;;)
+	{
+	}
+}
+
 void os_kernel()
 {
 	task_os();

07-ExterInterrupt/os.h

@@ -6,6 +6,7 @@
 #include "task.h"
 #include "timer.h"
 
+extern void panic(char *);
 extern void user_init();
 extern void os_kernel();
 extern int os_main(void);

07-ExterInterrupt/plic.c

@@ -1,5 +1,15 @@
 #include "os.h"
 
+// ref: https://github.com/qemu/qemu/blob/master/include/hw/riscv/virt.h
+// Intro: https://github.com/ianchen0119/AwesomeCS/wiki/2-5-RISC-V::%E4%B8%AD%E6%96%B7%E8%88%87%E7%95%B0%E5%B8%B8%E8%99%95%E7%90%86----PLIC-%E4%BB%8B%E7%B4%B9
+#define PLIC_BASE 0x0c000000L
+#define PLIC_PRIORITY(id) (PLIC_BASE + (id)*4)
+#define PLIC_PENDING(id) (PLIC_BASE + 0x1000 + ((id) / 32))
+#define PLIC_MENABLE(hart) (PLIC_BASE + 0x2000 + (hart)*0x80)
+#define PLIC_MTHRESHOLD(hart) (PLIC_BASE + 0x200000 + (hart)*0x1000)
+#define PLIC_MCLAIM(hart) (PLIC_BASE + 0x200004 + (hart)*0x1000)
+#define PLIC_MCOMPLETE(hart) (PLIC_BASE + 0x200004 + (hart)*0x1000)
+
 void plic_init()
 {
   int hart = r_tp();

07-ExterInterrupt/riscv.h

@@ -6,31 +6,29 @@
 #define reg_t uint32_t // RISCV32: register is 32bits
 // define reg_t as uint64_t // RISCV64: register is 64bits
 
-// ref: https://github.com/qemu/qemu/blob/master/include/hw/riscv/virt.h
-// Intro: https://github.com/ianchen0119/AwesomeCS/wiki/2-5-RISC-V::%E4%B8%AD%E6%96%B7%E8%88%87%E7%95%B0%E5%B8%B8%E8%99%95%E7%90%86----PLIC-%E4%BB%8B%E7%B4%B9
-#define PLIC_BASE 0x0c000000L
-#define PLIC_PRIORITY(id) (PLIC_BASE + (id)*4)
-#define PLIC_PENDING(id) (PLIC_BASE + 0x1000 + ((id) / 32))
-#define PLIC_MENABLE(hart) (PLIC_BASE + 0x2000 + (hart)*0x80)
-#define PLIC_MTHRESHOLD(hart) (PLIC_BASE + 0x200000 + (hart)*0x1000)
-#define PLIC_MCLAIM(hart) (PLIC_BASE + 0x200004 + (hart)*0x1000)
-#define PLIC_MCOMPLETE(hart) (PLIC_BASE + 0x200004 + (hart)*0x1000)
-
 // ref: https://www.activexperts.com/serial-port-component/tutorials/uart/
 #define UART 0x10000000L
-#define UART_THR (uint8_t *)(UART + 0x00) // THR:transmitter holding register
-#define UART_RHR (uint8_t *)(UART + 0x00) // RHR:Receive holding register
-#define UART_DLL (uint8_t *)(UART + 0x00) // LSB of Divisor Latch (write mode)
-#define UART_DLM (uint8_t *)(UART + 0x01) // MSB of Divisor Latch (write mode)
-#define UART_IER (uint8_t *)(UART + 0x01) // Interrupt Enable Register
-#define UART_LCR (uint8_t *)(UART + 0x03) // Line Control Register
-#define UART_LSR (uint8_t *)(UART + 0x05) // LSR:line status register
-#define UART_LSR_EMPTY_MASK 0x40          // LSR Bit 6: Transmitter empty; both the THR and LSR are empty
+#define UART_THR (volatile uint8_t *)(UART + 0x00) // THR:transmitter holding register
+#define UART_RHR (volatile uint8_t *)(UART + 0x00) // RHR:Receive holding register
+#define UART_DLL (volatile uint8_t *)(UART + 0x00) // LSB of Divisor Latch (write mode)
+#define UART_DLM (volatile uint8_t *)(UART + 0x01) // MSB of Divisor Latch (write mode)
+#define UART_IER (volatile uint8_t *)(UART + 0x01) // Interrupt Enable Register
+#define UART_LCR (volatile uint8_t *)(UART + 0x03) // Line Control Register
+#define UART_LSR (volatile uint8_t *)(UART + 0x05) // LSR:line status register
+#define UART_LSR_EMPTY_MASK 0x40                   // LSR Bit 6: Transmitter empty; both the THR and LSR are empty
 
 #define UART_REGR(reg) (*(reg))
 #define UART_REGW(reg, v) ((*reg) = (v))
 
 // ref: https://github.com/qemu/qemu/blob/master/include/hw/riscv/virt.h
+// enum {
+//     UART0_IRQ = 10,
+//     RTC_IRQ = 11,
+//     VIRTIO_IRQ = 1, /* 1 to 8 */
+//     VIRTIO_COUNT = 8,
+//     PCIE_IRQ = 0x20, /* 32 to 35 */
+//     VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
+// };
 #define UART0_IRQ 10
 #define VIRTIO_IRQ 1
 

07-ExterInterrupt/trap.c

@@ -12,7 +12,6 @@ void external_handler()
   int irq = plic_claim();
   if (irq == UART0_IRQ)
   {
-    lib_printf("irq is %d \n", irq);
     lib_isr();
   }
   else if (irq)

07-ExterInterrupt/user.c

@@ -4,16 +4,6 @@ int shared_var = 500;
 
 lock_t lock;
 
-void test()
-{
-	for (;;)
-	{
-		int ch = lib_getc();
-		if (ch >= 0)
-			lib_putc(ch);
-	}
-}
-
 void user_task0(void)
 {
 	lib_puts("Task0: Created!\n");
@@ -55,7 +45,7 @@ void user_task3(void)
 	lib_puts("Task3: Created!\n");
 	while (1)
 	{
-		lib_puts("Tryin to get the lock... \n");
+		lib_puts("Trying to get the lock... \n");
 		lock_acquire(&lock);
 		lib_puts("Get the lock!\n");
 		lock_free(&lock);
@@ -65,10 +55,9 @@ void user_task3(void)
 
 void user_init()
 {
-	// task_create(&test);
-	// lock_init(&lock);
+	lock_init(&lock);
 	task_create(&user_task0);
 	task_create(&user_task1);
-	// task_create(&user_task2);
-	// task_create(&user_task3);
+	task_create(&user_task2);
+	task_create(&user_task3);
 }

README.md

@@ -1,6 +1,6 @@
 [中文版說明文件](doc/tw)
 
-# mini-riscv-os 
+# mini-riscv-os
 
 Build a minimal multi-tasking OS kernel for RISC-V from scratch
 
@@ -10,10 +10,10 @@ However, [ccckmit](https://github.com/ccckmit) rewrite the project for RISC-V, a
 
 ## Build & Run on Windows 10
 
-* [git-bash](https://git-scm.com/download/win)
-* [FreedomStudio](https://www.sifive.com/software)
+- [git-bash](https://git-scm.com/download/win)
+- [FreedomStudio](https://www.sifive.com/software)
 
-After download and extract the FreedomStudio for windows. You have to set the system PATH to the folder of `riscv64-unknown-elf-gcc/bin` and `riscv-qemu/bin`. For example, I set PATH to the following folders. 
+After download and extract the FreedomStudio for windows. You have to set the system PATH to the folder of `riscv64-unknown-elf-gcc/bin` and `riscv-qemu/bin`. For example, I set PATH to the following folders.
 
 ```
 D:\install\FreedomStudio-2020-06-3-win64\SiFive\riscv64-unknown-elf-gcc-8.3.0-2020.04.1\bin
@@ -25,20 +25,24 @@ And you should start your git-bash to build the project. (It works for me in vsc
 
 ## Steps
 
-* [01-HelloOs](01-HelloOs)
+- [01-HelloOs](01-HelloOs)
   - Enable UART to print trivial greetings
-* [02-ContextSwitch](02-ContextSwitch)
+- [02-ContextSwitch](02-ContextSwitch)
   - Basic switch from OS to user task
-* [03-MultiTasking](03-MultiTasking)
+- [03-MultiTasking](03-MultiTasking)
   - Two user tasks are interatively switching
-* [04-TimerInterrupt](04-TimerInterrupt)
+- [04-TimerInterrupt](04-TimerInterrupt)
   - Enable SysTick for future scheduler implementation
-* [05-Preemptive](05-Preemptive)
+- [05-Preemptive](05-Preemptive)
   - Basic preemptive scheduling
+- [06-Spinlock](06-Spinlock)
+  - Lock implementation for protec critical sections
+- [07-ExternInterrupt](07-ExternInterrupt)
+  - Learing PLIC & external interruption
 
 ## Building and Verification
 
-* Changes the current working directory to the specified one and then
+- Changes the current working directory to the specified one and then
 
 ```
 make
@@ -53,6 +57,6 @@ in the `LICENSE` file.
 
 ## Reference
 
-* [Adventures in RISC-V](https://matrix89.github.io/writes/writes/experiments-in-riscv/)
-* [Xv6, a simple Unix-like teaching operating system](https://pdos.csail.mit.edu/6.828/2020/xv6.html)
-* [Basics of programming a UART](https://www.activexperts.com/serial-port-component/tutorials/uart/)
+- [Adventures in RISC-V](https://matrix89.github.io/writes/writes/experiments-in-riscv/)
+- [Xv6, a simple Unix-like teaching operating system](https://pdos.csail.mit.edu/6.828/2020/xv6.html)
+- [Basics of programming a UART](https://www.activexperts.com/serial-port-component/tutorials/uart/)