Use DedupGroup Phase in ChiselStage$

docs/src/cookbooks/hierarchy.md

@@ -352,11 +352,12 @@ class AddOne(val width: Int) extends Module {
   out := in + 1.U
 }
 
-class AddTwo(addOneDef: Definition[AddOne]) extends Module {
-  val i0 = Instance(addOneDef)
-  val i1 = Instance(addOneDef)
-  val in  = IO(Input(UInt(addOneDef.width.W)))
-  val out = IO(Output(UInt(addOneDef.width.W)))
+class AddTwo(addOneDef: => Definition[AddOne]) extends Module {
+  private val definition = addOneDef
+  val i0 = Instance(definition)
+  val i1 = Instance(definition)
+  val in  = IO(Input(UInt(definition.width.W)))
+  val out = IO(Output(UInt(definition.width.W)))
   i0.in := in
   i1.in := i0.out
   out   := i1.out

src/main/scala/circt/stage/ChiselStage.scala

@@ -57,6 +57,7 @@ object ChiselStage {
     Seq(
       Dependency[chisel3.stage.phases.Elaborate],
       Dependency[chisel3.stage.phases.Convert],
+      Dependency[chisel3.stage.phases.AddDedupGroupAnnotations],
       Dependency[circt.stage.phases.AddImplicitOutputFile],
       Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile],
       Dependency[circt.stage.phases.Checks],

src/test/scala-2/chiselTests/DedupSpec.scala

@@ -3,10 +3,11 @@
 package chiselTests
 
 import chisel3._
-import chisel3.util._
+import chisel3.util.{Counter, Decoupled, Queue}
 import chisel3.experimental.{annotate, dedupGroup}
 import chisel3.experimental.hierarchy.Definition
 import chisel3.properties.Class
+import circt.stage.ChiselStage
 import firrtl.transforms.DedupGroupAnnotation
 import chisel3.experimental.hierarchy._
 import chisel3.util.circt.PlusArgsValue
@@ -121,13 +122,20 @@ class DedupSpec extends ChiselFlatSpec {
     }) === 3)
   }
 
-  it should "work natively for desiredNames" in {
+  it should "work natively for desiredNames with ChiselStage (the class)" in {
     assert(countModules(compile {
       val top = new SharedConstantValDedupTopDesiredName
       top
     }) === 3)
   }
 
+  it should "work natively for desiredNames with ChiselStage$ (the object)" in {
+    assert(countModules(ChiselStage.emitSystemVerilog {
+      val top = new SharedConstantValDedupTopDesiredName
+      top
+    }) === 3)
+  }
+
   it should "error on conflicting dedup groups" in {
     a[Exception] should be thrownBy {
       compile {