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[ELF] Pass Ctx & to check*
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@MaskRay
MaskRay committed Oct 13, 2024
1 parent 0dbc85a commit 2c5dd03
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Showing 16 changed files with 182 additions and 180 deletions.
46 changes: 23 additions & 23 deletions lld/ELF/Arch/AArch64.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -484,17 +484,17 @@ void AArch64::relocate(uint8_t *loc, const Relocation &rel,
switch (rel.type) {
case R_AARCH64_ABS16:
case R_AARCH64_PREL16:
checkIntUInt(loc, val, 16, rel);
checkIntUInt(ctx, loc, val, 16, rel);
write16(ctx, loc, val);
break;
case R_AARCH64_ABS32:
case R_AARCH64_PREL32:
checkIntUInt(loc, val, 32, rel);
checkIntUInt(ctx, loc, val, 32, rel);
write32(ctx, loc, val);
break;
case R_AARCH64_PLT32:
case R_AARCH64_GOTPCREL32:
checkInt(loc, val, 32, rel);
checkInt(ctx, loc, val, 32, rel);
write32(ctx, loc, val);
break;
case R_AARCH64_ABS64:
Expand Down Expand Up @@ -535,13 +535,13 @@ void AArch64::relocate(uint8_t *loc, const Relocation &rel,
case R_AARCH64_ADR_PREL_PG_HI21:
case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
case R_AARCH64_TLSDESC_ADR_PAGE21:
checkInt(loc, val, 33, rel);
checkInt(ctx, loc, val, 33, rel);
[[fallthrough]];
case R_AARCH64_ADR_PREL_PG_HI21_NC:
write32AArch64Addr(loc, val >> 12);
break;
case R_AARCH64_ADR_PREL_LO21:
checkInt(loc, val, 21, rel);
checkInt(ctx, loc, val, 21, rel);
write32AArch64Addr(loc, val);
break;
case R_AARCH64_JUMP26:
Expand All @@ -555,14 +555,14 @@ void AArch64::relocate(uint8_t *loc, const Relocation &rel,
write32le(loc, 0x14000000);
[[fallthrough]];
case R_AARCH64_CALL26:
checkInt(loc, val, 28, rel);
checkInt(ctx, loc, val, 28, rel);
writeMaskedBits32le(loc, (val & 0x0FFFFFFC) >> 2, 0x0FFFFFFC >> 2);
break;
case R_AARCH64_CONDBR19:
case R_AARCH64_LD_PREL_LO19:
case R_AARCH64_GOT_LD_PREL19:
checkAlignment(loc, val, 4, rel);
checkInt(loc, val, 21, rel);
checkAlignment(ctx, loc, val, 4, rel);
checkInt(ctx, loc, val, 21, rel);
writeMaskedBits32le(loc, (val & 0x1FFFFC) << 3, 0x1FFFFC << 3);
break;
case R_AARCH64_LDST8_ABS_LO12_NC:
Expand All @@ -571,45 +571,45 @@ void AArch64::relocate(uint8_t *loc, const Relocation &rel,
break;
case R_AARCH64_LDST16_ABS_LO12_NC:
case R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC:
checkAlignment(loc, val, 2, rel);
checkAlignment(ctx, loc, val, 2, rel);
write32Imm12(loc, getBits(val, 1, 11));
break;
case R_AARCH64_LDST32_ABS_LO12_NC:
case R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC:
checkAlignment(loc, val, 4, rel);
checkAlignment(ctx, loc, val, 4, rel);
write32Imm12(loc, getBits(val, 2, 11));
break;
case R_AARCH64_LDST64_ABS_LO12_NC:
case R_AARCH64_LD64_GOT_LO12_NC:
case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
case R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC:
case R_AARCH64_TLSDESC_LD64_LO12:
checkAlignment(loc, val, 8, rel);
checkAlignment(ctx, loc, val, 8, rel);
write32Imm12(loc, getBits(val, 3, 11));
break;
case R_AARCH64_LDST128_ABS_LO12_NC:
case R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC:
checkAlignment(loc, val, 16, rel);
checkAlignment(ctx, loc, val, 16, rel);
write32Imm12(loc, getBits(val, 4, 11));
break;
case R_AARCH64_LD64_GOTPAGE_LO15:
checkAlignment(loc, val, 8, rel);
checkAlignment(ctx, loc, val, 8, rel);
write32Imm12(loc, getBits(val, 3, 14));
break;
case R_AARCH64_MOVW_UABS_G0:
checkUInt(loc, val, 16, rel);
checkUInt(ctx, loc, val, 16, rel);
[[fallthrough]];
case R_AARCH64_MOVW_UABS_G0_NC:
writeMaskedBits32le(loc, (val & 0xFFFF) << 5, 0xFFFF << 5);
break;
case R_AARCH64_MOVW_UABS_G1:
checkUInt(loc, val, 32, rel);
checkUInt(ctx, loc, val, 32, rel);
[[fallthrough]];
case R_AARCH64_MOVW_UABS_G1_NC:
writeMaskedBits32le(loc, (val & 0xFFFF0000) >> 11, 0xFFFF0000 >> 11);
break;
case R_AARCH64_MOVW_UABS_G2:
checkUInt(loc, val, 48, rel);
checkUInt(ctx, loc, val, 48, rel);
[[fallthrough]];
case R_AARCH64_MOVW_UABS_G2_NC:
writeMaskedBits32le(loc, (val & 0xFFFF00000000) >> 27,
Expand All @@ -622,7 +622,7 @@ void AArch64::relocate(uint8_t *loc, const Relocation &rel,
case R_AARCH64_MOVW_PREL_G0:
case R_AARCH64_MOVW_SABS_G0:
case R_AARCH64_TLSLE_MOVW_TPREL_G0:
checkInt(loc, val, 17, rel);
checkInt(ctx, loc, val, 17, rel);
[[fallthrough]];
case R_AARCH64_MOVW_PREL_G0_NC:
case R_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
Expand All @@ -631,7 +631,7 @@ void AArch64::relocate(uint8_t *loc, const Relocation &rel,
case R_AARCH64_MOVW_PREL_G1:
case R_AARCH64_MOVW_SABS_G1:
case R_AARCH64_TLSLE_MOVW_TPREL_G1:
checkInt(loc, val, 33, rel);
checkInt(ctx, loc, val, 33, rel);
[[fallthrough]];
case R_AARCH64_MOVW_PREL_G1_NC:
case R_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
Expand All @@ -640,7 +640,7 @@ void AArch64::relocate(uint8_t *loc, const Relocation &rel,
case R_AARCH64_MOVW_PREL_G2:
case R_AARCH64_MOVW_SABS_G2:
case R_AARCH64_TLSLE_MOVW_TPREL_G2:
checkInt(loc, val, 49, rel);
checkInt(ctx, loc, val, 49, rel);
[[fallthrough]];
case R_AARCH64_MOVW_PREL_G2_NC:
writeSMovWImm(loc, val >> 32);
Expand All @@ -649,11 +649,11 @@ void AArch64::relocate(uint8_t *loc, const Relocation &rel,
writeSMovWImm(loc, val >> 48);
break;
case R_AARCH64_TSTBR14:
checkInt(loc, val, 16, rel);
checkInt(ctx, loc, val, 16, rel);
writeMaskedBits32le(loc, (val & 0xFFFC) << 3, 0xFFFC << 3);
break;
case R_AARCH64_TLSLE_ADD_TPREL_HI12:
checkUInt(loc, val, 24, rel);
checkUInt(ctx, loc, val, 24, rel);
write32Imm12(loc, val >> 12);
break;
case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
Expand Down Expand Up @@ -682,7 +682,7 @@ void AArch64::relaxTlsGdToLe(uint8_t *loc, const Relocation &rel,
// movk x0, #0x10
// nop
// nop
checkUInt(loc, val, 32, rel);
checkUInt(ctx, loc, val, 32, rel);

switch (rel.type) {
case R_AARCH64_TLSDESC_ADD_LO12:
Expand Down Expand Up @@ -734,7 +734,7 @@ void AArch64::relaxTlsGdToIe(uint8_t *loc, const Relocation &rel,

void AArch64::relaxTlsIeToLe(uint8_t *loc, const Relocation &rel,
uint64_t val) const {
checkUInt(loc, val, 32, rel);
checkUInt(ctx, loc, val, 32, rel);

if (rel.type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21) {
// Generate MOVZ.
Expand Down
2 changes: 1 addition & 1 deletion lld/ELF/Arch/AMDGPU.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -167,7 +167,7 @@ void AMDGPU::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
break;
case R_AMDGPU_REL16: {
int64_t simm = (static_cast<int64_t>(val) - 4) / 4;
checkInt(loc, simm, 16, rel);
checkInt(ctx, loc, simm, 16, rel);
write16le(loc, simm);
break;
}
Expand Down
28 changes: 14 additions & 14 deletions lld/ELF/Arch/ARM.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -576,7 +576,7 @@ static void encodeLdrGroup(Ctx &ctx, uint8_t *loc, const Relocation &rel,
val = -val;
}
uint32_t imm = getRemAndLZForGroup(group, val).first;
checkUInt(loc, imm, 12, rel);
checkUInt(ctx, loc, imm, 12, rel);
write32(ctx, loc, (read32(ctx, loc) & 0xff7ff000) | opcode | imm);
}

Expand All @@ -594,7 +594,7 @@ static void encodeLdrsGroup(Ctx &ctx, uint8_t *loc, const Relocation &rel,
val = -val;
}
uint32_t imm = getRemAndLZForGroup(group, val).first;
checkUInt(loc, imm, 8, rel);
checkUInt(ctx, loc, imm, 8, rel);
write32(ctx, loc,
(read32(ctx, loc) & 0xff7ff0f0) | opcode | ((imm & 0xf0) << 4) |
(imm & 0xf));
Expand Down Expand Up @@ -622,7 +622,7 @@ void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
write32(ctx, loc, val);
break;
case R_ARM_PREL31:
checkInt(loc, val, 31, rel);
checkInt(ctx, loc, val, 31, rel);
write32(ctx, loc, (read32(ctx, loc) & 0x80000000) | (val & ~0x80000000));
break;
case R_ARM_CALL: {
Expand All @@ -639,7 +639,7 @@ void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
stateChangeWarning(ctx, loc, rel.type, *rel.sym);
if (rel.sym->isFunc() ? bit0Thumb : isBlx) {
// The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1'
checkInt(loc, val, 26, rel);
checkInt(ctx, loc, val, 26, rel);
write32(ctx, loc,
0xfa000000 | // opcode
((val & 2) << 23) | // H
Expand All @@ -655,23 +655,23 @@ void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
case R_ARM_JUMP24:
case R_ARM_PC24:
case R_ARM_PLT32:
checkInt(loc, val, 26, rel);
checkInt(ctx, loc, val, 26, rel);
write32(ctx, loc,
(read32(ctx, loc) & ~0x00ffffff) | ((val >> 2) & 0x00ffffff));
break;
case R_ARM_THM_JUMP8:
// We do a 9 bit check because val is right-shifted by 1 bit.
checkInt(loc, val, 9, rel);
checkInt(ctx, loc, val, 9, rel);
write16(ctx, loc, (read32(ctx, loc) & 0xff00) | ((val >> 1) & 0x00ff));
break;
case R_ARM_THM_JUMP11:
// We do a 12 bit check because val is right-shifted by 1 bit.
checkInt(loc, val, 12, rel);
checkInt(ctx, loc, val, 12, rel);
write16(ctx, loc, (read32(ctx, loc) & 0xf800) | ((val >> 1) & 0x07ff));
break;
case R_ARM_THM_JUMP19:
// Encoding T3: Val = S:J2:J1:imm6:imm11:0
checkInt(loc, val, 21, rel);
checkInt(ctx, loc, val, 21, rel);
write16(ctx, loc,
(read16(ctx, loc) & 0xfbc0) | // opcode cond
((val >> 10) & 0x0400) | // S
Expand Down Expand Up @@ -708,7 +708,7 @@ void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
if (!ctx.arg.armJ1J2BranchEncoding) {
// Older Arm architectures do not support R_ARM_THM_JUMP24 and have
// different encoding rules and range due to J1 and J2 always being 1.
checkInt(loc, val, 23, rel);
checkInt(ctx, loc, val, 23, rel);
write16(ctx, loc,
0xf000 | // opcode
((val >> 12) & 0x07ff)); // imm11
Expand All @@ -723,7 +723,7 @@ void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
[[fallthrough]];
case R_ARM_THM_JUMP24:
// Encoding B T4, BL T1, BLX T2: Val = S:I1:I2:imm10:imm11:0
checkInt(loc, val, 25, rel);
checkInt(ctx, loc, val, 25, rel);
write16(ctx, loc,
0xf000 | // opcode
((val >> 14) & 0x0400) | // S
Expand Down Expand Up @@ -829,7 +829,7 @@ void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
imm = -imm;
sub = 0x00a0;
}
checkUInt(loc, imm, 12, rel);
checkUInt(ctx, loc, imm, 12, rel);
write16(ctx, loc, (read16(ctx, loc) & 0xfb0f) | sub | (imm & 0x800) >> 1);
write16(ctx, loc + 2,
(read16(ctx, loc + 2) & 0x8f00) | (imm & 0x700) << 4 |
Expand All @@ -843,8 +843,8 @@ void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
// bottom bit to recover S + A - Pa.
if (rel.sym->isFunc())
val &= ~0x1;
checkUInt(loc, val, 10, rel);
checkAlignment(loc, val, 4, rel);
checkUInt(ctx, loc, val, 10, rel);
checkAlignment(ctx, loc, val, 4, rel);
write16(ctx, loc, (read16(ctx, loc) & 0xff00) | (val & 0x3fc) >> 2);
break;
case R_ARM_THM_PC12: {
Expand All @@ -861,7 +861,7 @@ void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
imm12 = -imm12;
u = 0;
}
checkUInt(loc, imm12, 12, rel);
checkUInt(ctx, loc, imm12, 12, rel);
write16(ctx, loc, read16(ctx, loc) | u);
write16(ctx, loc + 2, (read16(ctx, loc + 2) & 0xf000) | imm12);
break;
Expand Down
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