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Syntactic checks

Verilog: assignment to 1-bit LHSs require truncation #3610

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Verilog: assignment to 1-bit LHSs require truncation

Verilog: assignment to 1-bit LHSs require truncation #3610

Triggered via pull request December 23, 2025 15:20
@kroeningkroening
opened #1514
wire_with_assignment1
Status Success
Total duration 1m 27s
Artifacts –

syntax-checks.yaml

on: pull_request
check-clang-format
1m 25s
check-clang-format
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