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Merge pull request #1132 from diffblue/buechi-sva-s_until_with
SVA-to-Buechi: release/until operators
2 parents e3179b5 + de56d24 commit 1284a3d

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Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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CORE
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../../verilog/SVA/sva_until1.sv
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--buechi
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^\[main\.p0\] always \(main.a until_with main.b\): REFUTED$
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^\[main\.p1\] always \(main.a until main.b\): REFUTED$
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^\[main\.p2\] always \(main.a s_until main.b\): REFUTED$
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^EXIT=10$
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^SIGNAL=0$
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--
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^warning: ignoring
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--

src/temporal-logic/ltl_sva_to_string.cpp

Lines changed: 17 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -267,13 +267,27 @@ ltl_sva_to_stringt::rec(const exprt &expr, modet mode)
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PRECONDITION(mode == PROPERTY);
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return infix(" U ", expr, mode);
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}
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else if(expr.id() == ID_sva_until)
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{
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PRECONDITION(mode == PROPERTY);
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return infix(" W ", expr, mode);
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}
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else if(expr.id() == ID_sva_s_until_with)
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{
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// This is release with swapped operands
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// This is strong release with swapped operands
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PRECONDITION(mode == PROPERTY);
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auto &until_with = to_sva_s_until_with_expr(expr);
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auto R = R_exprt{until_with.rhs(), until_with.lhs()}; // swapped
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return rec(R, mode);
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auto new_expr =
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strong_R_exprt{until_with.rhs(), until_with.lhs()}; // swapped
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return infix(" M ", new_expr, mode);
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}
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else if(expr.id() == ID_sva_until_with)
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{
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// This is weak release with swapped operands
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PRECONDITION(mode == PROPERTY);
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auto &until_with = to_sva_until_with_expr(expr);
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auto new_expr = R_exprt{until_with.rhs(), until_with.lhs()}; // swapped
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return infix(" R ", new_expr, mode);
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}
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else if(
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expr.id() == ID_sva_weak || expr.id() == ID_sva_strong ||

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