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Full-duplex I2S opeeration on these platforms requires "I2Sext" peripherals that work alongside the SPI/I2S peripherals. This PR attempts to add support for these peripherals, in support of enabling full-duplex operation at the embassy-stm32 layer.

I tried following the directions in the README, invoking ./d extract-all for I2S2ext and I2S3ext. This produced a few dozen YAML files, of which there were two unique classes modulo renaming of fields. I called these i2sext_v1.yaml for the F4 family and _v2.yaml for the F3 family (following release date order). I added lines to perimap.rs which ought to have caught the relevant peripherals.

However, I hit a roadblock here. The entries in PERIMAP never hit, apparently because the I2Sext peripherals don't appear in the chip XML in data/cubedb, from which the ChipGroup values are generated. Those XML files do contain the pin definitions that the ext-peripherals require (e.g., in STM32F405RGTx.xml, pin PB4 has I2S3_ext_SD).

I would appreciate guidance on how to move forward here. I suspect that the I2Sext peripherals might need special handling like the I2S peripherals, but this is exceeding the bounds of my knowledge here.

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embassy-ci bot commented Sep 24, 2025

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