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ttrocc: Add misc + cmdbuf builtins #4

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b38c461
ttrocc: Add extension and base misc builtins
CohenArthur Oct 14, 2025
81f9fbd
ttrocc: Add remaining misc builtins, add cmdbuf builtins
CohenArthur Oct 14, 2025
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4 changes: 4 additions & 0 deletions gcc/common/config/riscv/riscv-common.cc
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Expand Up @@ -192,6 +192,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"xttwh", ISA_SPEC_CLASS_NONE, 1, 0},
{"xttbh", ISA_SPEC_CLASS_NONE, 1, 0},

{"xttrocc", ISA_SPEC_CLASS_NONE, 1, 0},

/* Terminate the list. */
{NULL, ISA_SPEC_CLASS_NONE, 0, 0}
};
Expand Down Expand Up @@ -1145,6 +1147,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =

{"xttwh", &gcc_options::x_riscv_tt_flags, MASK_TT_WH},
{"xttbh", &gcc_options::x_riscv_tt_flags, MASK_TT_BH},

{"xttrocc", &gcc_options::x_riscv_xttrocc, MASK_XTTROCC},

{NULL, NULL, 0}
};
Expand Down
10 changes: 9 additions & 1 deletion gcc/config/riscv/riscv-builtins.cc
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Expand Up @@ -98,6 +98,9 @@ AVAIL (hard_float, TARGET_HARD_FLOAT)
AVAIL (wormhole, TARGET_RVTT_WH)
AVAIL (blackhole, TARGET_RVTT_BH)
AVAIL (sfpu, (TARGET_RVTT_WH || TARGET_RVTT_BH))
// FIXME: This should be `AVAIL (rocc, TARGET_XTTROCC)`
// once the x extension support is added
AVAIL (rocc, 1)

/* Construct a riscv_builtin_description from the given arguments.

Expand Down Expand Up @@ -142,9 +145,11 @@ tree v64SF_type_node;
/* Argument types. */
#define RISCV_ATYPE_VOID void_type_node
#define RISCV_ATYPE_SI intSI_type_node
#define RISCV_ATYPE_DI intDI_type_node
#define RISCV_ATYPE_HI intHI_type_node
#define RISCV_ATYPE_QI intQI_type_node
#define RISCV_ATYPE_USI unsigned_intSI_type_node
#define RISCV_ATYPE_UDI unsigned_intDI_type_node
#define RISCV_ATYPE_UHI unsigned_intHI_type_node
#define RISCV_ATYPE_UQI unsigned_intQI_type_node
#define RISCV_ATYPE_V64SF v64SF_type_node
Expand All @@ -171,13 +176,16 @@ tree v64SF_type_node;
#define RISCV_FTYPE_ATYPES8(A, B, C, D, E, F, G, H, I) \
RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C, RISCV_ATYPE_##D, RISCV_ATYPE_##E, RISCV_ATYPE_##F, RISCV_ATYPE_##G, RISCV_ATYPE_##H, RISCV_ATYPE_##I

static const int first_sfpu_builtin = 2;
static const int first_sfpu_builtin = 28;

static const struct riscv_builtin_description riscv_builtins[] = {
DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float),
DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float),

// If you add builtins here, update the start of the sfpu builtins above

#include "ttrocc.def"

/* Tenstorrent SFPU builtins */
#define RVTT_BUILTIN(op, fmt, fl, dap, mp, sched, nip, nim, nis) DIRECT_RVTT_BUILTIN(op, fmt, sfpu),
#define RVTT_NO_TGT_BUILTIN(op, fmt, fl, dap, mp, sched, nip, nim, nis) DIRECT_RVTT_NO_TARGET_BUILTIN(op, fmt, sfpu),
Expand Down
7 changes: 7 additions & 0 deletions gcc/config/riscv/riscv-ftypes.def
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Expand Up @@ -32,12 +32,15 @@ DEF_RISCV_FTYPE (1, (VOID, USI))
/* Tenstorrent SFPU definitions */
DEF_RISCV_FTYPE (0, (VOID))
DEF_RISCV_FTYPE (0, (V64SF))
DEF_RISCV_FTYPE (0, (UDI))

DEF_RISCV_FTYPE (1, (V64SF, USI))
DEF_RISCV_FTYPE (1, (V64SF, V64SF))
DEF_RISCV_FTYPE (1, (VOID, V64SF))
DEF_RISCV_FTYPE (1, (VOID, UDI))
DEF_RISCV_FTYPE (1, (POINTER, POINTER))
DEF_RISCV_FTYPE (1, (USI, USI))
DEF_RISCV_FTYPE (1, (UDI, UDI))
DEF_RISCV_FTYPE (1, (USI, UHI))
DEF_RISCV_FTYPE (1, (USI, UQI))
DEF_RISCV_FTYPE (1, (SI, SI))
Expand All @@ -46,6 +49,8 @@ DEF_RISCV_FTYPE (1, (SI, QI))

DEF_RISCV_FTYPE (2, (VOID, USI, USI))
DEF_RISCV_FTYPE (2, (VOID, V64SF, USI))
DEF_RISCV_FTYPE (2, (VOID, UDI, UDI))
DEF_RISCV_FTYPE (2, (UDI, UDI, UDI))
DEF_RISCV_FTYPE (2, (V64SF, V64SF, V64SF))
DEF_RISCV_FTYPE (2, (V64SF, USI, USI))
DEF_RISCV_FTYPE (2, (V64SF, USI, UHI))
Expand All @@ -58,6 +63,8 @@ DEF_RISCV_FTYPE (3, (VOID, USI, USI, USI))
DEF_RISCV_FTYPE (3, (VOID, V64SF, USI, USI))
DEF_RISCV_FTYPE (3, (VOID, USI, V64SF, USI))
DEF_RISCV_FTYPE (3, (VOID, V64SF, V64SF, USI))
DEF_RISCV_FTYPE (3, (VOID, UDI, UDI, UDI))
DEF_RISCV_FTYPE (3, (UDI, UDI, UDI, UDI))
DEF_RISCV_FTYPE (3, (USI, USI, USI, USI))
DEF_RISCV_FTYPE (3, (USI, V64SF, V64SF, USI))
DEF_RISCV_FTYPE (3, (V64SF, USI, V64SF, USI))
Expand Down
1 change: 1 addition & 0 deletions gcc/config/riscv/riscv.md
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Expand Up @@ -2871,6 +2871,7 @@
(include "pic.md")
(include "generic.md")
(include "sifive-7.md")
(include "ttrocc.md")

(include "tt/rvtt.md")
(include "tt/rvtt-wh.md")
Expand Down
6 changes: 6 additions & 0 deletions gcc/config/riscv/riscv.opt
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Expand Up @@ -212,6 +212,12 @@ int riscv_zvl_flags
TargetVariable
int riscv_tt_flags

TargetVariable
int riscv_xttrocc

; FIXME: We need to implement this properly using the option instead
Mask(XTTROCC) Var(riscv_xttrocc)

Enum
Name(isa_spec_class) Type(enum riscv_isa_spec_class)
Supported ISA specs (for use with the -misa-spec= option):
Expand Down
38 changes: 38 additions & 0 deletions gcc/config/riscv/ttrocc.def
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@@ -0,0 +1,38 @@
RISCV_BUILTIN (ttrocc_dbg_postcode, "ttrocc_dbg_postcode", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV_VOID_FTYPE_UDI, rocc),
RISCV_BUILTIN (ttrocc_noc_fence, "ttrocc_noc_fence", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV_VOID_FTYPE, rocc),

RISCV_BUILTIN (ttrocc_llk_intf_write, "ttrocc_llk_intf_write", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV_VOID_FTYPE_UDI_UDI, rocc),
RISCV_BUILTIN (ttrocc_llk_intf_read, "ttrocc_llk_intf_read", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI, rocc),

RISCV_BUILTIN (ttrocc_fds_intf_write, "ttrocc_fds_intf_write", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV_VOID_FTYPE_UDI_UDI, rocc),
RISCV_BUILTIN (ttrocc_fds_intf_read, "ttrocc_fds_intf_read", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI, rocc),

RISCV_BUILTIN (ttrocc_cmdbuf_wr_reg, "ttrocc_cmdbuf_wr_reg", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV_VOID_FTYPE_UDI_UDI_UDI, rocc),
RISCV_BUILTIN (ttrocc_cmdbuf_rd_reg, "ttrocc_cmdbuf_rd_reg", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI_UDI, rocc),

RISCV_BUILTIN (ttrocc_cmdbuf_get_vc_space, "ttrocc_cmdbuf_get_vc_space", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI, rocc),
RISCV_BUILTIN (ttrocc_cmdbuf_get_vc_space_vc, "ttrocc_cmdbuf_get_vc_space_vc", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI_UDI, rocc),

RISCV_BUILTIN (ttrocc_cmdbuf_wr_sent, "ttrocc_cmdbuf_wr_sent", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI, rocc),
RISCV_BUILTIN (ttrocc_cmdbuf_wr_sent_trid, "ttrocc_cmdbuf_wr_sent_trid", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI_UDI, rocc),

RISCV_BUILTIN (ttrocc_cmdbuf_tr_ack, "ttrocc_cmdbuf_tr_ack", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI, rocc),
RISCV_BUILTIN (ttrocc_cmdbuf_tr_ack_trid, "ttrocc_cmdbuf_tr_ack_trid", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI_UDI, rocc),

RISCV_BUILTIN (ttrocc_cmdbuf_reset, "ttrocc_cmdbuf_reset", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV_VOID_FTYPE_UDI, rocc),

RISCV_BUILTIN (ttrocc_cmdbuf_idma_get_vc_space, "ttrocc_cmdbuf_idma_get_vc_space", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI, rocc),
RISCV_BUILTIN (ttrocc_cmdbuf_idma_get_vc_space_vc, "ttrocc_cmdbuf_idma_get_vc_space_vc", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI_UDI, rocc),

RISCV_BUILTIN (ttrocc_cmdbuf_idma_tr_ack, "ttrocc_cmdbuf_idma_tr_ack", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI, rocc),
RISCV_BUILTIN (ttrocc_cmdbuf_idma_tr_ack_trid, "ttrocc_cmdbuf_idma_tr_ack_trid", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI_UDI, rocc),

RISCV_BUILTIN (ttrocc_cmdbuf_issue_trans, "ttrocc_cmdbuf_issue_trans", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV_VOID_FTYPE_UDI, rocc),
RISCV_BUILTIN (ttrocc_cmdbuf_issue_inline_trans, "ttrocc_cmdbuf_issue_inline_trans", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV_VOID_FTYPE_UDI_UDI, rocc),
RISCV_BUILTIN (ttrocc_cmdbuf_issue_inline_addr_trans, "ttrocc_cmdbuf_issue_inline_addr_trans", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV_VOID_FTYPE_UDI_UDI_UDI, rocc),

RISCV_BUILTIN (ttrocc_cmdbuf_issue_read1_trans, "ttrocc_cmdbuf_issue_read1_trans", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV_VOID_FTYPE_UDI_UDI, rocc),
RISCV_BUILTIN (ttrocc_cmdbuf_issue_read2_trans, "ttrocc_cmdbuf_issue_read2_trans", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV_VOID_FTYPE_UDI_UDI_UDI, rocc),

RISCV_BUILTIN (ttrocc_cmdbuf_issue_write1_trans, "ttrocc_cmdbuf_issue_write1_trans", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV_VOID_FTYPE_UDI_UDI, rocc),
RISCV_BUILTIN (ttrocc_cmdbuf_issue_write2_trans, "ttrocc_cmdbuf_issue_write2_trans", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV_VOID_FTYPE_UDI_UDI_UDI, rocc),
238 changes: 238 additions & 0 deletions gcc/config/riscv/ttrocc.md
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@@ -0,0 +1,238 @@
;; Machine description for Tenstorrent ROCC Intrinsics.
;; Copyright (C) 2025 Tenstorrent Inc.

;; This file is part of GCC.

;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.

;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.

;; TT rocc extension

;; FIXME: We need to use a proper target string like TARGET_XVTTROCC but once the 15.1 update is complete
;; for now, keep the empty string

(define_c_enum "unspecv" [
UNSPECV_NOC_FENCE
UNSPECV_DBG_POSTCODE
UNSPECV_LLK_INTF_WRITE
UNSPECV_LLK_INTF_READ
UNSPECV_FDS_INTF_WRITE
UNSPECV_FDS_INTF_READ
UNSPECV_CMDBUF_WR_REG
UNSPECV_CMDBUF_RD_REG
UNSPECV_CMDBUF_GET_VC_SPACE
UNSPECV_CMDBUF_GET_VC_SPACE_VC
UNSPECV_CMDBUF_WR_SENT
UNSPECV_CMDBUF_WR_SENT_TRID
UNSPECV_CMDBUF_TR_ACK
UNSPECV_CMDBUF_TR_ACK_TRID
UNSPECV_CMDBUF_RESET
UNSPECV_CMDBUF_IDMA_GET_VC_SPACE
UNSPECV_CMDBUF_IDMA_GET_VC_SPACE_VC
UNSPECV_CMDBUF_IDMA_TR_ACK
UNSPECV_CMDBUF_IDMA_TR_ACK_TRID
UNSPECV_CMDBUF_ISSUE_TRANS
UNSPECV_CMDBUF_ISSUE_INLINE_TRANS
UNSPECV_CMDBUF_ISSUE_INLINE_ADDR_TRANS
UNSPECV_CMDBUF_ISSUE_READ1_TRANS
UNSPECV_CMDBUF_ISSUE_READ2_TRANS
UNSPECV_CMDBUF_ISSUE_WRITE1_TRANS
UNSPECV_CMDBUF_ISSUE_WRITE2_TRANS
])

(define_insn "riscv_ttrocc_noc_fence"
[(unspec_volatile [(const_int 0)] UNSPECV_NOC_FENCE)]
""
"tt.rocc.noc_fence")

(define_insn "riscv_ttrocc_dbg_postcode"
[(unspec_volatile [(match_operand:DI 0 "register_operand")] UNSPECV_DBG_POSTCODE)]
""
"tt.rocc.dbg_postcode\t%0")

(define_insn "riscv_ttrocc_llk_intf_write"
[(unspec_volatile [(match_operand:DI 0 "const_int_operand")
(match_operand:DI 1 "const_int_operand")] UNSPECV_LLK_INTF_WRITE)]
""
"tt.rocc.llk_intf_write\t%0,%1")

(define_insn "riscv_ttrocc_llk_intf_read"
[(unspec_volatile [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "const_int_operand")] UNSPECV_LLK_INTF_READ)]
""
"tt.rocc.llk_intf_read\t%1")

(define_insn "riscv_ttrocc_fds_intf_write"
[(unspec_volatile [(match_operand:DI 0 "const_int_operand")
(match_operand:DI 1 "const_int_operand")] UNSPECV_FDS_INTF_WRITE)]
""
"tt.rocc.fds_intf_write\t%0,%1")

(define_insn "riscv_ttrocc_fds_intf_read"
[(unspec_volatile [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "const_int_operand")] UNSPECV_FDS_INTF_READ)]
""
"tt.rocc.fds_intf_read\t%1")

(define_insn "riscv_ttrocc_cmdbuf_wr_reg"
[(unspec_volatile [(match_operand:DI 0 "const_int_operand")
(match_operand:DI 1 "const_int_operand")
(match_operand:DI 2 "register_operand")
] UNSPECV_CMDBUF_WR_REG)]
""
;; We hardcode two extra unused registers per the HW engineers' request
"tt.rocc.cmdbuf_wr_reg\tx0,%0,%1,%2,x0")

(define_insn "riscv_ttrocc_cmdbuf_rd_reg"
[(unspec_volatile [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "const_int_operand")
(match_operand:DI 2 "const_int_operand")
] UNSPECV_CMDBUF_RD_REG)
(return)]
""
;; We hardcode three extra unused registers per the HW engineers' request
"tt.rocc.cmdbuf_rd_reg\tx0,%1,%2,x0,x0")

(define_insn "riscv_ttrocc_cmdbuf_get_vc_space"
[(unspec_volatile [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "const_int_operand")
] UNSPECV_CMDBUF_GET_VC_SPACE)]
""
"tt.rocc.cmdbuf_get_vc_space\t%1")

(define_insn "riscv_ttrocc_cmdbuf_get_vc_space_vc"
[(unspec_volatile [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "const_int_operand")
(match_operand:DI 2 "register_operand")
] UNSPECV_CMDBUF_GET_VC_SPACE_VC)]
""
"tt.rocc.cmdbuf_get_vc_space_vc\t%1,%2")

(define_insn "riscv_ttrocc_cmdbuf_wr_sent"
[(unspec_volatile [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "const_int_operand")
] UNSPECV_CMDBUF_WR_SENT)]
""
"tt.rocc.cmdbuf_wr_sent\t%1")

(define_insn "riscv_ttrocc_cmdbuf_wr_sent_trid"
[(unspec_volatile [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "const_int_operand")
(match_operand:DI 2 "register_operand")
] UNSPECV_CMDBUF_WR_SENT_TRID)]
""
"tt.rocc.cmdbuf_wr_sent_trid\t%1,%2")

(define_insn "riscv_ttrocc_cmdbuf_tr_ack"
[(unspec_volatile [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "const_int_operand")
] UNSPECV_CMDBUF_TR_ACK)]
""
"tt.rocc.cmdbuf_tr_ack\t%1")

(define_insn "riscv_ttrocc_cmdbuf_tr_ack_trid"
[(unspec_volatile [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "const_int_operand")
(match_operand:DI 2 "register_operand")
] UNSPECV_CMDBUF_TR_ACK_TRID)]
""
"tt.rocc.cmdbuf_tr_ack_trid\t%1,%2")

(define_insn "riscv_ttrocc_cmdbuf_reset"
[(unspec_volatile [(match_operand:DI 0 "const_int_operand")
] UNSPECV_CMDBUF_RESET)]
""
"tt.rocc.cmdbuf_reset\t%0")

(define_insn "riscv_ttrocc_cmdbuf_idma_get_vc_space"
[(unspec_volatile [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "const_int_operand")
] UNSPECV_CMDBUF_IDMA_GET_VC_SPACE)]
""
"tt.rocc.cmdbuf_idma_get_vc_space\t%1")

(define_insn "riscv_ttrocc_cmdbuf_idma_get_vc_space_vc"
[(unspec_volatile [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "const_int_operand")
(match_operand:DI 2 "register_operand")
] UNSPECV_CMDBUF_IDMA_GET_VC_SPACE_VC)]
""
"tt.rocc.cmdbuf_idma_get_vc_space_vc\t%1,%2")


(define_insn "riscv_ttrocc_cmdbuf_idma_tr_ack"
[(unspec_volatile [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "const_int_operand")
] UNSPECV_CMDBUF_IDMA_TR_ACK)]
""
"tt.rocc.cmdbuf_idma_tr_ack\t%1")

(define_insn "riscv_ttrocc_cmdbuf_idma_tr_ack_trid"
[(unspec_volatile [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "const_int_operand")
(match_operand:DI 2 "register_operand")
] UNSPECV_CMDBUF_IDMA_TR_ACK_TRID)]
""
"tt.rocc.cmdbuf_idma_tr_ack_trid\t%1,%2")

(define_insn "riscv_ttrocc_cmdbuf_issue_trans"
[(unspec_volatile [(match_operand:DI 0 "const_int_operand")
] UNSPECV_CMDBUF_ISSUE_TRANS)]
""
"tt.rocc.cmdbuf_issue_trans\t%0")

(define_insn "riscv_ttrocc_cmdbuf_issue_inline_trans"
[(unspec_volatile [(match_operand:DI 0 "const_int_operand")
(match_operand:DI 1 "register_operand")
] UNSPECV_CMDBUF_ISSUE_INLINE_TRANS)]
""
"tt.rocc.cmdbuf_issue_inline_trans\t%0,%1")

(define_insn "riscv_ttrocc_cmdbuf_issue_inline_addr_trans"
[(unspec_volatile [(match_operand:DI 0 "const_int_operand")
(match_operand:DI 1 "register_operand")
(match_operand:DI 2 "register_operand")
] UNSPECV_CMDBUF_ISSUE_INLINE_ADDR_TRANS)]
""
"tt.rocc.cmdbuf_issue_inline_addr_trans\t%0,%1,%2")

(define_insn "riscv_ttrocc_cmdbuf_issue_read1_trans"
[(unspec_volatile [(match_operand:DI 0 "const_int_operand")
(match_operand:DI 1 "register_operand")
] UNSPECV_CMDBUF_ISSUE_READ1_TRANS)]
""
"tt.rocc.cmdbuf_issue_read1_trans\t%0,%1")

(define_insn "riscv_ttrocc_cmdbuf_issue_read2_trans"
[(unspec_volatile [(match_operand:DI 0 "const_int_operand")
(match_operand:DI 1 "register_operand")
(match_operand:DI 2 "register_operand")
] UNSPECV_CMDBUF_ISSUE_READ2_TRANS)]
""
"tt.rocc.cmdbuf_issue_read2_trans\t%0,%1,%2")

(define_insn "riscv_ttrocc_cmdbuf_issue_write1_trans"
[(unspec_volatile [(match_operand:DI 0 "const_int_operand")
(match_operand:DI 1 "register_operand")
] UNSPECV_CMDBUF_ISSUE_WRITE1_TRANS)]
""
"tt.rocc.cmdbuf_issue_write1_trans\t%0,%1")

(define_insn "riscv_ttrocc_cmdbuf_issue_write2_trans"
[(unspec_volatile [(match_operand:DI 0 "const_int_operand")
(match_operand:DI 1 "register_operand")
(match_operand:DI 2 "register_operand")
] UNSPECV_CMDBUF_ISSUE_WRITE2_TRANS)]
""
"tt.rocc.cmdbuf_issue_write2_trans\t%0,%1,%2")
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