Documentation fixes and renamed quartus_workflow.py to just workflow.py

Author: fe-wickham

autogen_quartus.py

@@ -3,7 +3,7 @@
 import logging
 
 from quartus.workflow_config import WorkflowConfig
-from quartus.quartus_workflow import execute_quartus_workflow
+from quartus.workflow import execute_quartus_workflow
 
 
 def main(inputFilename, working_dir, log_to_file=False):
@@ -17,6 +17,7 @@ def main(inputFilename, working_dir, log_to_file=False):
     finally:
         logger.info("exit")
 
+
 def init_logging(debugLevel, log_to_file=False):
     logger = logging.getLogger('autogen_quartus')
 
@@ -34,10 +35,9 @@ def init_logging(debugLevel, log_to_file=False):
     logger.setLevel(debugLevel)
     return logger
 
+
 def parseargs():
-    """
-    Parse commandline input arguments.
-    """
+    """Parse commandline input arguments."""
     parser = argparse.ArgumentParser(
         description="Executes the quartus workflow, from creating a system to compiling the project made around that system")
     parser.add_argument('-j', '--json',

device_drivers/gen_makefile.py

@@ -23,8 +23,7 @@
 import argparse
 
 def create_kbuild(path, model_name):
-    """
-    Create Kbuild file for kernel module compilation. 
+    """Create Kbuild file for kernel module compilation.
 
     This creates a minimal Kbuild file so we can build our 
     autogenerated kernel modules. Our kernel modules rely on 
@@ -50,8 +49,7 @@ def create_kbuild(path, model_name):
 
 
 def create_makefile(path):
-    """
-    Create Makefile for kernel module compilation. 
+    """Create Makefile for kernel module compilation.
 
     This function writes the Makefile to the kernel module directory.
 
@@ -76,9 +74,7 @@ def create_makefile(path):
 
 
 def parseargs():
-    """
-    Parse commandline input arguments.
-    """
+    """Parse commandline input arguments."""
     parser = argparse.ArgumentParser(description=\
         "Generate files used for building kernel modules.")
     parser.add_argument('path',
@@ -91,8 +87,7 @@ def parseargs():
 
 # NOTE: path MUST contain a trailing slash so this code can be platform independent
 def main(path, model_name):
-    """
-    Run the program and build files needed for building a kernel module
+    """Run the program and build files needed for building a kernel module.
 
     Inputs:
         path = path, including trailing slash, to the kernel module location

ipcore/create_hw_tcl.py

@@ -261,9 +261,7 @@ def create_source_connection_point(dataplane_config):
 
 
 def parseargs():
-    """
-    Parse commandline input arguments.
-    """
+    """Parse commandline input arguments."""
     parser = argparse.ArgumentParser(
         description="Generates a Platform Design/Qsys component as _hw.tcl file")
     parser.add_argument('-c', '--config',

quartus/quartus_templates.py

@@ -55,9 +55,19 @@
 """
 
 
-class quartus_templates:
+class QuartusTemplates:
+    """Generate templates for Quartus workflow."""
 
     def __init__(self, num_custom_components, baseAddress):
+        """Initialize QuartusTemplates.
+
+        Parameters
+        ----------
+        num_custom_components : [type]
+            [description]
+        baseAddress : [type]
+            [description]
+        """
         self.custom_components_added = 0
         self.num_custom_components = num_custom_components
         self.de10_components_base_address = 20  # Format is 0x0020

quartus/target.py

@@ -1,3 +1,9 @@
+"""This module provides tuples to describe target configurations of quartus_workflow.
+
+* Target      tuple to define information needed about a target
+* Audiomini   instance of Target tuple to describe the target configuration for a DE-10 Nano with an Audiomini
+* Audioblade  instance of Target tuple to describe the configuration for an Audioblade
+"""
 import collections
 
 Target = collections.namedtuple('Target',
@@ -6,19 +12,19 @@
                                  'axi_master_name', 'audio_in', 'audio_out', 'clock_name', 'top_level_vhdl_file'])
 
 Audiomini = Target(name='audiomini', system_name='audiomini_system', device_family='Cyclone V',
-              device='5CSEBA6U23I7', base_qsys_file='soc_base_system.qsys', base_proj_tcl_file='audiomini_proj.tcl',
-              files_list=['Audiomini.vhd',
-                          'audiomini_system/synthesis/audiomini_system.qip'],
-              top_level_vhdl_file='Audiomini.vhd', original_system='soc_system', base_address='20', axi_master_name='hps.h2f_lw_axi_master',
-              audio_in='FE_Qsys_AD1939_Audio_Mini_v1_0.Line_In', audio_out='FE_Qsys_AD1939_Audio_Mini_v1_0.Headphone_Out',
-              clock_name='clk_hps'
-              )
-              
+                   device='5CSEBA6U23I7', base_qsys_file='soc_base_system.qsys', base_proj_tcl_file='audiomini_proj.tcl',
+                   files_list=['Audiomini.vhd',
+                               'audiomini_system/synthesis/audiomini_system.qip'],
+                   top_level_vhdl_file='Audiomini.vhd', original_system='soc_system', base_address='20', axi_master_name='hps.h2f_lw_axi_master',
+                   audio_in='FE_Qsys_AD1939_Audio_Mini_v1_0.Line_In', audio_out='FE_Qsys_AD1939_Audio_Mini_v1_0.Headphone_Out',
+                   clock_name='clk_hps'
+                   )
+
 Audioblade = Target(name='audioblade', system_name='audioblade_system', device_family='Arria 10',
-                 device='10AS066H2F34I1HG', base_qsys_file='som_system.qsys', base_proj_tcl_file='audioblade_proj.tcl',
-                 files_list=['A10SoM_System.vhd',
-                             'audioblade_system/audioblade_system.qip', 'pll.qsys'],
-                 top_level_vhdl_file='A10SoM_System.vhd', original_system='som_system', base_address='20',
-                 axi_master_name='arria10_hps_0.h2f_lw_axi_master', audio_in='FE_Qsys_AD1939_Audio_Research_v1_0.Line_In',
-                 audio_out='FE_Qsys_AD1939_Audio_Research_v1_0.Headphone_Out', clock_name='clk_1'
-                 )
+                    device='10AS066H2F34I1HG', base_qsys_file='som_system.qsys', base_proj_tcl_file='audioblade_proj.tcl',
+                    files_list=['A10SoM_System.vhd',
+                                'audioblade_system/audioblade_system.qip', 'pll.qsys'],
+                    top_level_vhdl_file='A10SoM_System.vhd', original_system='som_system', base_address='20',
+                    axi_master_name='arria10_hps_0.h2f_lw_axi_master', audio_in='FE_Qsys_AD1939_Audio_Research_v1_0.Line_In',
+                    audio_out='FE_Qsys_AD1939_Audio_Research_v1_0.Headphone_Out', clock_name='clk_1'
+                    )